公开(公告)号：US07876893B2

公开(公告)日：2011-01-25

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US20100329446A1

公开(公告)日：2010-12-30

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US20070030031A1

公开(公告)日：2007-02-08

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands receivese first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or impresses the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收第一和第二双轨信号，其包括计算周期中的数据值和预充电周期中的预充电值，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入处感测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时，才施加预充电值。

公开(公告)号：US07881465B2

公开(公告)日：2011-02-01

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H04L9/28

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or stops impressing the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收包括计算周期中的数据值和预充电周期中的预充电值的第一和第二双轨信号，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入端检测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时停止施加预充电值。

公开(公告)号：US07342423B2

公开(公告)日：2008-03-11

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。

公开(公告)号：US20070035332A1

公开(公告)日：2007-02-15

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。