公开(公告)号：US07876893B2

公开(公告)日：2011-01-25

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US20100329446A1

公开(公告)日：2010-12-30

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。

公开(公告)号：US20070030031A1

公开(公告)日：2007-02-08

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands receivese first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or impresses the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收第一和第二双轨信号，其包括计算周期中的数据值和预充电周期中的预充电值，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入处感测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时，才施加预充电值。

公开(公告)号：US07881465B2

公开(公告)日：2011-02-01

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H04L9/28

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or stops impressing the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收包括计算周期中的数据值和预充电周期中的预充电值的第一和第二双轨信号，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入端检测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时停止施加预充电值。

公开(公告)号：US07342423B2

公开(公告)日：2008-03-11

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。

公开(公告)号：US20070035332A1

公开(公告)日：2007-02-15

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。

公开(公告)号：US20070047292A1

公开(公告)日：2007-03-01

申请号：US11444295

申请日：2006-05-31

申请人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

发明人： Joerg Berthold ,  Dieter Draxelmayr ,  Winfried Kamp ,  Michael Kund ,  Tim Schoenauer

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C14/009

摘要： Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.

摘要翻译： 具有以非易失性方式电可编程的第一电阻器的非易失性存储器单元，以非易失性方式电可编程的第二电阻器，连接在第一电阻器和工作电位之间的第一漏电流减少元件和第二漏电流 连接在第二电阻和工作电位之间的减少元件。

公开(公告)号：US20050204274A1

公开(公告)日：2005-09-15

申请号：US11063953

申请日：2005-02-23

申请人： Winfried Kamp ,  Siegmar Koppe

发明人： Winfried Kamp ,  Siegmar Koppe

IPC分类号： G06F11/00 ,  G06F11/10 ,  G11C29/00 ,  H03M13/00

CPC分类号： G11C15/04 ,  G06F11/1048 ,  G11C15/00 ,  G11C2029/0411

摘要： A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload data word to be stored, with the parity checking circuit being formed from four transistors of the same conductance type. The parity checking circuit has a detector, which automatically detects the change in an information state of a memory cell. The detector is in the form of an automatic state device and has a number of catch latches.

摘要翻译： 奇偶校验电路被设计用于可内容寻址存储器单元的连续奇偶校验，并且被配置为使得在奇偶校验期间，每个数据字的奇偶校验步骤的数量与原始有效载荷数据字中的位数相同 存储奇偶校验电路由相同电导型的四个晶体管形成。 奇偶校验电路具有检测器，其自动检测存储器单元的信息状态的变化。 检测器是自动状态设备的形式，并具有多个锁存器。

公开(公告)号：US08331163B2

公开(公告)日：2012-12-11

申请号：US12876560

申请日：2010-09-07

申请人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

发明人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

IPC分类号： G11C7/10

CPC分类号： G11C29/10 ,  G11C7/10 ,  G11C11/41 ,  G11C19/28 ,  G11C29/022 ,  G11C29/32

摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

摘要翻译： 一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。 一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。 输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构 通过使用例如常规扫描测试方法的第二测试阶段。

公开(公告)号：US07816198B2

公开(公告)日：2010-10-19

申请号：US11775504

申请日：2007-07-10

申请人： Martin Ostermayr ,  Winfried Kamp ,  Anton Huber

发明人： Martin Ostermayr ,  Winfried Kamp ,  Anton Huber

IPC分类号： H01L29/94

CPC分类号： H01L21/823807 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件具有至少一个NMOS器件和设置在衬底上的至少一个PMOS器件。 NMOS器件的电子通道与第一方向对准。 PMOS器件的空穴通道与形成相对于第一方向的锐角的不同的第二方向对齐。