公开(公告)号：US20110110169A1

公开(公告)日：2011-05-12

申请号：US12911575

申请日：2010-10-25

申请人： Antonio GIAMBARTINO ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio GIAMBARTINO ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C7/06

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈电的非反相输入端子和连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US06885584B2

公开(公告)日：2005-04-26

申请号：US10748447

申请日：2003-12-30

申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C2216/30

摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

公开(公告)号：US20050041471A1

公开(公告)日：2005-02-24

申请号：US10748447

申请日：2003-12-30

申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

IPC分类号： G11C16/12 ,  G11C16/10

CPC分类号： G11C16/12 ,  G11C2216/30

摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

公开(公告)号：US07843738B2

公开(公告)日：2010-11-30

申请号：US11713067

申请日：2007-02-28

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C16/06

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US08254194B2

公开(公告)日：2012-08-28

申请号：US12911575

申请日：2010-10-25

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。

公开(公告)号：US20080013381A1

公开(公告)日：2008-01-17

申请号：US11713067

申请日：2007-02-28

申请人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

发明人： Antonio Giambartino ,  Michele La Placa ,  Ignazio Martines

IPC分类号： G11C11/4091 ,  H03F3/45

CPC分类号： G11C7/067 ,  G11C7/04 ,  G11C16/28 ,  G11C2207/063

摘要： A reading circuit for a semiconductor memory, comprising: a circuital branch adapted to be electrically coupled to a bit line which is connected to a memory cell to be read; an evaluation circuit adapted to sense a cell electric current flowing through the bit line during a sensing phase of a reading operation of the data stored into the memory cell, the evaluation circuit comprising a negative feedback control loop adapted to control the potential of the bit line during the sensing phase, the control loop comprising a differential amplifier having an inverting input terminal operatively connected to the bit line, a non-inverting input terminal fed by a first reference potential, and a feedback circuital path connected between an output of the differential amplifier and the inverting input, wherein the feedback circuital path is adapted to conduct a measure current corresponding to the cell electric current, and comprises current/voltage conversion means for converting the measure current into a corresponding voltage. The conversion means of the feedback circuital path comprises at least one first transistor arranged to conduct the measure current, and biasing means adapted to bias the at least one first transistor so as to emulate the behavior of a resistor.

摘要翻译： 一种用于半导体存储器的读取电路，包括：电路分支，其适于电耦合到连接到要读取的存储器单元的位线; 评估电路，适于在存储在存储单元中的数据的读取操作的感测阶段期间感测流过位线的单元电流，该评估电路包括负反馈控制回路，适于控制位线的电位 在感测阶段期间，控制回路包括差分放大器，其具有可操作地连接到位线的反相输入端子，由第一参考电位馈送的非反相输入端子以及连接在差分放大器的输出端之间的反馈电路 和反相输入端，其中反馈电路路径适于传导对应于电池电流的测量电流，并且包括用于将测量电流转换成相应电压的电流/电压转换装置。 反馈电路的转换装置包括布置成传导测量电流的至少一个第一晶体管，以及适于偏置至少一个第一晶体管以便模拟电阻器的行为的偏置装置。