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    FAST PAGE PROGRAMMING ARCHITECTURE AND METHOD IN A NON-VOLATILE MEMORY DEVICE WITH AN SPI INTERFACE
    1.
    发明申请
    FAST PAGE PROGRAMMING ARCHITECTURE AND METHOD IN A NON-VOLATILE MEMORY DEVICE WITH AN SPI INTERFACE 有权
    具有SPI接口的非易失性存储器件中的快速编程架构和方法

    公开(公告)号：US20050041471A1

    公开(公告)日：2005-02-24

    申请号：US10748447

    申请日：2003-12-30

    申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

    发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

    IPC分类号： G11C16/12 ,  G11C16/10

    CPC分类号： G11C16/12 ,  G11C2216/30

    摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

    摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

    Fast page programming architecture and method in a non-volatile memory device with an SPI interface
    2.
    发明授权
    Fast page programming architecture and method in a non-volatile memory device with an SPI interface 有权
    具有SPI接口的非易失性存储器件中的快速页面编程架构和方法

    公开(公告)号：US06885584B2

    公开(公告)日：2005-04-26

    申请号：US10748447

    申请日：2003-12-30

    申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

    发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

    IPC分类号： G11C16/12 ,  G11C16/04

    CPC分类号： G11C16/12 ,  G11C2216/30

    摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

    摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

    Structure for updating a block of memory cells in a flash memory device with erase and program operation reduction
    3.
    发明授权
    Structure for updating a block of memory cells in a flash memory device with erase and program operation reduction 有权
    用于在擦除和编程操作减少的情况下更新闪速存储器件中的存储单元块的结构

    公开(公告)号：US06922362B2

    公开(公告)日：2005-07-26

    申请号：US10686552

    申请日：2003-10-15

    申请人： Antonino La Malfa ,  Salvatore Poli ,  Paolino Schillaci

    发明人： Antonino La Malfa ,  Salvatore Poli ,  Paolino Schillaci

    IPC分类号： G11C16/12 ,  G11C16/00

    CPC分类号： G11C16/12

    摘要： An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

    摘要翻译： 一种用于更新闪速存储器件中的存储单元块的电子电路结构，所述存储器单元存储当前值，其中所述结构包括用于接收待写入到所述存储器单元的新值的数据锁存器，用于擦除所述存储器单元的控制器 同时存储单元的块，以及耦合到控制器的编程负载组和用于单独编程存储器单元的数据锁存器; 所述结构还包括耦合到所述控制器的控制逻辑器，用于使得所述控制器能够根据所述新值和所述当前值之间的比较启用所述编程负载组。

    Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards
    4.
    发明授权
    Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards 有权
    用于在主板上的可用寻址区域中映射和选择具有LPC串行通信接口的非易失性存储器件的自动解码方法

    公开(公告)号：US07231487B2

    公开(公告)日：2007-06-12

    申请号：US10623474

    申请日：2003-07-18

    申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

    发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G11C8/06 ,  G06F12/0653 ,  G11C15/00

    摘要： The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

    摘要翻译： 本发明涉及一种用于映射和选择在主板上的可用寻址区域中具有LPC串行通信接口的非易失性存储器件的自动解码方法。 逻辑结构被结合在存储器件中，其允许正确的解码将存储器寻址到可寻址区域的顶部或相同区域的底部，即在两种可能的情况下。 该逻辑包含非易失性寄存器，其信息存储在内容地址存储器中，以使得可寻址存储器区域中的存储器自动映射。

    Circuit for generating an internal enabling signal for an output buffer of a memory
    6.
    发明授权
    Circuit for generating an internal enabling signal for an output buffer of a memory 有权
    用于产生用于存储器的输出缓冲器的内部使能信号的电路

    公开(公告)号：US07535774B2

    公开(公告)日：2009-05-19

    申请号：US11337030

    申请日：2006-01-20

    申请人： Antonino La Malfa ,  Marco Messina

    发明人： Antonino La Malfa ,  Marco Messina

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1051 ,  G11C7/1066

    摘要： A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.

    摘要翻译： 电路用于根据用于使能存储器和输出数据的外部命令的功能来产生用于存储器的输出缓冲器的内部使能信号。 当存储器被读取时以及当存储器的数据的读取操作结束时，可以用外部命令输入电路以启用存储器和内部产生的标志信号。 当存储器被使能并且来自存储器的数据的读取操作结束时，电路可以产生具有空逻辑值的第一中间信号。 该电路还可以在第一中间信号和允许存储器的外部命令与用于输出数据的外部命令之间的逻辑或之间产生内部使能信号作为逻辑NOR。

    Enhancement of power on reliability in a dual power supply digital device with down converter
    8.
    发明授权
    Enhancement of power on reliability in a dual power supply digital device with down converter 有权
    在具有降压转换器的双电源数字设备中增强可靠性的功率

    公开(公告)号：US07336117B2

    公开(公告)日：2008-02-26

    申请号：US11457634

    申请日：2006-07-14

    申请人： Antonino La Malfa ,  Marco Messina

    发明人： Antonino La Malfa ,  Marco Messina

    IPC分类号： H03L5/00 ,  H03K1/175

    CPC分类号： H03K3/356104

    摘要： A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

    摘要翻译： 双电源数字设备包括用于将外部施加的电源电压转换为调节的第一电源电压的下变频器，以为数字设备的逻辑电路的核心部分供电。 第二电源电压源提供第二电源电压以为数字设备的I / O焊盘的输入缓冲器供电。 电压转换器锁存级可以以调节的转换的第一电源电压供电，用于将存在于数字设备的相应I / O焊盘上的逻辑值的存储的反相副本复制到相应的第二输入逻辑缓冲器供电的输入节点上 处于调节核心电源电压。 器件还可以包括晶体管，其具有将第二缓冲器的输入节点耦合到调节下变换的核心电源电压的导通阈值，晶体管具有连接到第二电源的控制栅极。

    Method for soft-programming an electrically erasable nonvolatile memory device, and an electrically erasable nonvolatile memory device implementing the soft-programming method
    9.
    发明授权
    Method for soft-programming an electrically erasable nonvolatile memory device, and an electrically erasable nonvolatile memory device implementing the soft-programming method 有权
    用于软编程电可擦除非易失存储器件的方法，以及实现软编程方法的电可擦除非易失性存储器件

    公开(公告)号：US07120062B2

    公开(公告)日：2006-10-10

    申请号：US10779856

    申请日：2004-02-17

    申请人： Antonino La Malfa ,  Marco Messina

    发明人： Antonino La Malfa ,  Marco Messina

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： Described herein is a method for soft-programming an electrically erasable nonvolatile memory device, wherein soft-programming is carried out with a soft-programming multiplicity equal to twice that used for writing data in the memory device until the current absorbed during soft-programming is smaller than or equal to the maximum current which is available for writing operations and which can be generated within the memory device, and with a soft-programming multiplicity equal to the one used for writing data in the memory device in the case where the current absorbed during soft-programming with double multiplicity is greater than the maximum current which is available for writing operations and which can be generated within the memory device.

    摘要翻译： 这里描述了一种用于软编程电可擦除非易失性存储器件的方法，其中以软编程多重性等于用于在存储器件中写入数据的两倍的软编程来执行软编程，直到在软编程期间吸收的电流为 小于或等于可用于写入操作并且可以在存储器件内产生的最大电流，并且在电流吸收的情况下具有与用于在存储器件中写入数据的软编程多重性相等的软编程倍数 在具有双重多重性的软编程期间，大于可用于写入操作的最大电流，并且可以在存储器件内生成。

    Random bit sequence generator
    10.
    发明授权
    Random bit sequence generator 有权
    随机位序发生器

    公开(公告)号：US07099906B2

    公开(公告)日：2006-08-29

    申请号：US10270020

    申请日：2002-10-11

    申请人： Marco Messina ,  Antonino La Malfa

    发明人： Marco Messina ,  Antonino La Malfa

    IPC分类号： G06F1/02 ,  G06J1/00

    CPC分类号： H03K3/84 ,  H03B29/00

    摘要： A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.

    摘要翻译： 随机比特序列发生器包括偏置电路，由偏置电路偏置的噪声电压信号的源;放大级，产生代表有噪声电压信号的唯一非零频率（AC）分量的放大信号;以及 与放大级级联的输出级，其产生放大信号功能的随机位序列。 发生器还对不期望的低频干扰分量进行滤波，因为放大级包括输入低通滤波器，其将噪声电压信号的零（DC）分量馈送到差分放大器的输入之一，输入到 其被馈送未经滤波的噪声电压信号。