公开(公告)号：US20050041471A1

公开(公告)日：2005-02-24

申请号：US10748447

申请日：2003-12-30

申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Salvatore Polizzi

IPC分类号： G11C16/12 ,  G11C16/10

CPC分类号： G11C16/12 ,  G11C2216/30

摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

公开(公告)号：US06975559B2

公开(公告)日：2005-12-13

申请号：US10452762

申请日：2003-05-30

申请人： Maurizio Perroni ,  Salvatore Polizzi ,  Salvatore Poli

发明人： Maurizio Perroni ,  Salvatore Polizzi ,  Salvatore Poli

IPC分类号： G11C11/16 ,  G11C16/32 ,  G11C29/14 ,  G11C11/00

CPC分类号： G11C29/1201 ,  G11C11/16 ,  G11C16/04 ,  G11C16/32 ,  G11C29/14 ,  G11C2029/2602

摘要： The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal.In this way, at each cycle of the control signal two memory locations, instead of one as in the prior art, are read.

摘要翻译： 本发明涉及一种用于测试具有至少一个并行通信接口的非易失性存储器件的方法，以及具有相应读取，改变和擦除电路的常规非易失性存储单元矩阵，其中在测试过程期间，读取模式 进入用于在产生相应的ATD信号的控制信号的上升沿读取存储器位置。 在本发明中有利的是，在控制信号的下降沿也开始后续的读取步骤。 以这种方式，在控制信号的每个周期，读取两个存储器位置，而不是现有技术中的一个。

公开(公告)号：US06892269B2

公开(公告)日：2005-05-10

申请号：US10271352

申请日：2002-10-15

申请人： Salvatore Polizzi ,  Salvatore Poli ,  Maurizio Perroni

发明人： Salvatore Polizzi ,  Salvatore Poli ,  Maurizio Perroni

IPC分类号： G11C7/10 ,  G11C16/08 ,  G11C16/26 ,  G06F12/00

CPC分类号： G11C7/1075 ,  G11C16/08 ,  G11C16/26 ,  G11C2207/107 ,  G11C2216/30

摘要： A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

摘要翻译： 非易失性存储器件可以串行模式和并行模式工作。 非易失性存储器件的架构基于已经存在于标准存储器中的结构，但是包括某些修改。 这些修改包括为各种存储器访问阶段（即，写入和读取数据）添加定时状态机，以及添加内部总线和相关逻辑电路，用于在非易失性存储器中禁用标准存储器的内部地址总线 设备以串行模式运行。

公开(公告)号：US07231487B2

公开(公告)日：2007-06-12

申请号：US10623474

申请日：2003-07-18

申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonino La Malfa

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C8/06 ,  G06F12/0653 ,  G11C15/00

摘要： The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

摘要翻译： 本发明涉及一种用于映射和选择在主板上的可用寻址区域中具有LPC串行通信接口的非易失性存储器件的自动解码方法。 逻辑结构被结合在存储器件中，其允许正确的解码将存储器寻址到可寻址区域的顶部或相同区域的底部，即在两种可能的情况下。 该逻辑包含非易失性寄存器，其信息存储在内容地址存储器中，以使得可寻址存储器区域中的存储器自动映射。

公开(公告)号：US06885584B2

公开(公告)日：2005-04-26

申请号：US10748447

申请日：2003-12-30

申请人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

发明人： Paolino Schillaci ,  Salvatore Poli ,  Antonio Giambartino ,  Antonino La Malfa ,  Slavatore Polizzi

IPC分类号： G11C16/12 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C2216/30

摘要： A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

摘要翻译： 电路架构和方法在配备有存储单元矩阵和SPI串行通信接口的非易失性存储器电子设备中执行页面编程，以及与单元矩阵相关联的电路部分，并负责寻址，解码，读取， 写入和擦除存储单元内容。 有利地，提供缓冲存储器组以通过接口以伪串行模式在页面编程期间存储和输出数据。 一次一个位地执行数据锁存，并且一次以至少两个字节进行以下的输出。

公开(公告)号：US06996697B2

公开(公告)日：2006-02-07

申请号：US10371221

申请日：2003-02-21

申请人： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

发明人： Salvatore Poli ,  Paolino Schillaci ,  Salvatore Polizzi

IPC分类号： G06F12/00

CPC分类号： G11C16/22

摘要： The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

公开(公告)号：US06922362B2

公开(公告)日：2005-07-26

申请号：US10686552

申请日：2003-10-15

申请人： Antonino La Malfa ,  Salvatore Poli ,  Paolino Schillaci

发明人： Antonino La Malfa ,  Salvatore Poli ,  Paolino Schillaci

IPC分类号： G11C16/12 ,  G11C16/00

CPC分类号： G11C16/12

摘要： An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

摘要翻译： 一种用于更新闪速存储器件中的存储单元块的电子电路结构，所述存储器单元存储当前值，其中所述结构包括用于接收待写入到所述存储器单元的新值的数据锁存器，用于擦除所述存储器单元的控制器 同时存储单元的块，以及耦合到控制器的编程负载组和用于单独编程存储器单元的数据锁存器; 所述结构还包括耦合到所述控制器的控制逻辑器，用于使得所述控制器能够根据所述新值和所述当前值之间的比较启用所述编程负载组。