Semiconductor device having a field effect transistor and a method of manufacturing such a device
    1.
    发明授权
    Semiconductor device having a field effect transistor and a method of manufacturing such a device 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号:US06420755B1

    公开(公告)日:2002-07-16

    申请号:US09709663

    申请日:2000-11-10

    IPC分类号: H01L2976

    摘要: A field effect transistor (T) of the (quasi-)vertical type, which means that in the semiconductor body (10) of the transistor (T), a source (1) and a drain (3) are positioned (approximately) above each other and are separated from each other by the channel region (2), which is connected to a gate region (4), each one of said regions being connected to a connection conductor (6, 7, 11) joining a connection region (7, 8, 12). The connection regions (7, 8) of the source (1) and the gate (4) are situated on top of the semiconductor body (10). The semiconductor body (10) is provided with a through-hole (9) at least one wall of which is covered with a conductive layer (11), which is connected to the drain (3), and which forms the connection conductor (11) of the drain (3) and which is connected to the connection region (12) for the drain (3) situated on top of the semiconductor body (10). In this way, the transistor (T) is very well suited for surface mounting and is also very easy to manufacture. The through-hole (9) can be made by means of a cheap technique, such as laser cutting or sandblasting. Moreover, the transistor (T) is insensitive to the thickness of the channel region (2), which, in addition, may be comparatively thick. This simplifies the manufacture thereof and renders the transistor (T) suitable for both high power and high voltage applications. An additional advantage is that the transistor (T) can be manufactured without using a comparatively expensive epitaxial process.

    摘要翻译: (准)垂直型的场效应晶体管(T),这意味着在晶体管(T)的半导体本体(10)中,源(1)和漏极(3)位于(大约)上方 彼此分离,并且通过连接到栅极区域(4)的沟道区域(2)彼此分离,每个所述区域连接到连接导体(6,7,11),所述连接导体(6,7,11)连接到连接区域 7,8,12)。 源极(1)和栅极(4)的连接区域(7,8)位于半导体本体(10)的顶部。 半导体本体(10)设置有通孔(9),其至少一个壁被导电层(11)覆盖,该导电层连接到漏极(3),并形成连接导体(11) ),并且连接到位于半导体本体(10)的顶部上的用于漏极(3)的连接区域(12)。 以这种方式,晶体管(T)非常适合于表面安装,并且也非常容易制造。 通孔(9)可以通过诸如激光切割或喷砂的廉价技术制成。 此外,晶体管(T)对沟道区域(2)的厚度不敏感,此外,其可以相对较厚。 这简化了其制造,并且使晶体管(T)适合于高功率和高电压应用。 另外的优点是可以在不使用相对昂贵的外延工艺的情况下制造晶体管(T)。