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1.发明授权Low power scan design and delay fault testing technique using first level supply gating 失效低功耗扫描设计和延时故障测试技术采用一级电源门控公开(公告)号：US07319343B2
公开(公告)日：2008-01-15
申请号：US11099386
申请日：2005-04-05
IPC分类号： H03K19/173 , G01R31/28
CPC分类号： G01R31/31858
摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。
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2.发明申请Low power scan design and delay fault testing technique using first level supply gating 失效低功耗扫描设计和延时故障测试技术采用一级电源门控公开(公告)号：US20060220679A1
公开(公告)日：2006-10-05
申请号：US11099386
申请日：2005-04-05
IPC分类号： H03K19/173
CPC分类号： G01R31/31858
摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。
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