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9 条记录 (耗时 0.01 秒)

    Sense amplifier circuit
    1.
    发明申请
    Sense amplifier circuit 失效

    公开(公告)号：US20070171748A1

    公开(公告)日：2007-07-26

    申请号：US11337348

    申请日：2006-01-23

    申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

    发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

    IPC分类号： G11C7/02

    CPC分类号： G11C7/065 ,  G11C11/413

    摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

    Low power scan design and delay fault testing technique using first level supply gating
    2.
    发明授权
    Low power scan design and delay fault testing technique using first level supply gating 失效
    低功耗扫描设计和延时故障测试技术采用一级电源门控

    公开(公告)号：US07319343B2

    公开(公告)日：2008-01-15

    申请号：US11099386

    申请日：2005-04-05

    申请人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    发明人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    IPC分类号： H03K19/173 ,  G01R31/28

    CPC分类号： G01R31/31858

    摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

    摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。

    Apparatus and methods for determining memory device faults
    3.
    发明申请
    Apparatus and methods for determining memory device faults 有权
    用于确定存储器件故障的装置和方法

    公开(公告)号：US20070242538A1

    公开(公告)日：2007-10-18

    申请号：US11404667

    申请日：2006-04-14

    申请人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    发明人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50016

    摘要： A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

    摘要翻译： 用于确定存储器件中的故障的测试电路。 测试电路包括：读取电路，被配置为在第一时刻和第二时刻读取存储器件中的存储单元内容。 测试电路包括比较第一和第二时刻的内容的比较器。 如果内容不同，则比较器指示发生故障。 测试方法也用于确定存储器单元中是否发生故障。

    Apparatus and methods for determining memory device faults
    4.
    发明授权
    Apparatus and methods for determining memory device faults 有权
    用于确定存储器件故障的装置和方法

    公开(公告)号：US07548473B2

    公开(公告)日：2009-06-16

    申请号：US11404667

    申请日：2006-04-14

    申请人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    发明人： Qikai Chen ,  Swarup Bhunia ,  Hamid Mahmoodi ,  Kaushik Roy

    IPC分类号： G11C7/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/50016

    摘要： A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.

    摘要翻译： 用于确定存储器件中的故障的测试电路。 测试电路包括：读取电路，被配置为在第一时刻和第二时刻读取存储器件中的存储单元内容。 测试电路包括比较第一和第二时刻的内容的比较器。 如果内容不同，则比较器指示发生故障。 测试方法也用于确定存储器单元中是否发生故障。

    Self-repairing technique in nano-scale SRAM to reduce parametric failures
    5.
    发明授权
    Self-repairing technique in nano-scale SRAM to reduce parametric failures 失效
    纳米级SRAM中的自修复技术可减少参数故障

    公开(公告)号：US07508697B1

    公开(公告)日：2009-03-24

    申请号：US11746448

    申请日：2007-05-09

    申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Keejong Kim ,  Kaushik Roy

    发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Keejong Kim ,  Kaushik Roy

    IPC分类号： G11C11/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/02 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/5006

    摘要： A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die Vt process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die Vt process corner, thereby reducing possible access and write failures.

    摘要翻译： 一种自修复SRAM和一种减少SRAM中参数故障的方法。 采用片内泄漏或延迟监测器来检测晶片间Vt过程角，响应于此，SRAM应用自适应体偏置以减少管芯中参数故障的数量并提高记忆产量。 实施例包括用于在存在低的晶片间Vt处理角的情况下将反向偏置（RBB）施加到SRAM阵列的电路，从而减少可能的读取和保持故障，并且在存在时向阵列应用前向偏置（FBB） 的高间隔Vt处理角，从而减少可能的访问和写入失败。

    Sense amplifier circuit
    7.
    发明授权
    Sense amplifier circuit 失效
    感应放大电路

    公开(公告)号：US07304903B2

    公开(公告)日：2007-12-04

    申请号：US11337348

    申请日：2006-01-23

    申请人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

    发明人： Saibal Mukhopadhyay ,  Hamid Mahmoodi ,  Kaushik Roy

    IPC分类号： G11C7/00

    CPC分类号： G11C7/065 ,  G11C11/413

    摘要： A sense amplifier circuit includes a first double-gate metal oxide semiconductor field effect transistor (DGMOSFET) having a first gate defining a first input to the circuit, a second gate and an output being coupled to a first output of the circuit and a second DGMOSFET having a first gate defining a second input of the circuit, a second gate connected to the output of the first DGMOSFET and an output connected to the second gate of the first DGMOSFET, the output of the second DGMOSFET being coupled to a second output of the circuit.

    摘要翻译： 读出放大器电路包括具有限定到电路的第一输入的第一栅极的第一双栅极金属氧化物半导体场效应晶体管（DGMOSFET），耦合到该电路的第一输出的第二栅极和输出端以及第二DGMOSFET 具有限定电路的第二输入的第一栅极，连接到第一DGMOSFET的输出的第二栅极和连接到第一DGMOSFET的第二栅极的输出端，第二DGMOSFET的输出耦合到第二DGMOSFET的第二输出端 电路。

    Low power scan design and delay fault testing technique using first level supply gating
    8.
    发明申请
    Low power scan design and delay fault testing technique using first level supply gating 失效
    低功耗扫描设计和延时故障测试技术采用一级电源门控

    公开(公告)号：US20060220679A1

    公开(公告)日：2006-10-05

    申请号：US11099386

    申请日：2005-04-05

    申请人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    发明人： Swarup Bhunia ,  Hamid Mahmoodi ,  Arijit Raychowhury ,  Saibal Mukhopadhyay ,  Kaushik Roy

    IPC分类号： H03K19/173

    CPC分类号： G01R31/31858

    摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.

    摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。