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1.发明申请Low power scan design and delay fault testing technique using first level supply gating 失效低功耗扫描设计和延时故障测试技术采用一级电源门控公开(公告)号：US20060220679A1
公开(公告)日：2006-10-05
申请号：US11099386
申请日：2005-04-05
IPC分类号： H03K19/173
CPC分类号： G01R31/31858
摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。
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2.发明申请Synthesis approach for active leakage power reduction using dynamic supply gating 有权使用动态电源门控进行有源漏电功率降低的综合方法公开(公告)号：US20070016808A1
公开(公告)日：2007-01-18
申请号：US11450711
申请日：2006-06-09
申请人： Swarup Bhunia , Nilanjan Banerjee , Hamid Mahmoodi , Qikai Chen , Kaushik Roy
发明人： Swarup Bhunia , Nilanjan Banerjee , Hamid Mahmoodi , Qikai Chen , Kaushik Roy
CPC分类号： H03K19/0016
摘要： A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.
摘要翻译： 一种逻辑合成方法，用于将电源门控应用于其主动操作模式中的通用逻辑电路的空闲部分，以减少功率需求及由此产生的电路。 利用香农膨胀来确定通用逻辑电路的空闲部分和有效部分。
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公开(公告)号：US08402401B2
公开(公告)日：2013-03-19
申请号：US12942675
申请日：2010-11-09
CPC分类号： G06F17/505 , G06F21/75 , G09C1/00 , H04L2209/16
摘要： One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.
摘要翻译： 一个实施例提供了一种用于保护集成电路芯片设计的方法。 该方法可以包括在存储器中存储包括一组节点的集成电路核心的电路描述，并从该组节点中选择多个修改节点。 可以将顺序结构插入电路描述中以提供修改的电路描述，利用多个修改节点作为输入的顺序结构。 修改后的电路描述可以存储在存储器中。
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公开(公告)号：US07548473B2
公开(公告)日：2009-06-16
申请号：US11404667
申请日：2006-04-14
申请人： Qikai Chen , Swarup Bhunia , Hamid Mahmoodi , Kaushik Roy
发明人： Qikai Chen , Swarup Bhunia , Hamid Mahmoodi , Kaushik Roy
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50016
摘要： A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.
摘要翻译： 用于确定存储器件中的故障的测试电路。 测试电路包括：读取电路，被配置为在第一时刻和第二时刻读取存储器件中的存储单元内容。 测试电路包括比较第一和第二时刻的内容的比较器。 如果内容不同，则比较器指示发生故障。 测试方法也用于确定存储器单元中是否发生故障。
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5.发明授权Synthesis approach for active leakage power reduction using dynamic supply gating 有权使用动态电源门控进行有源漏电功率降低的综合方法公开(公告)号：US07454738B2
公开(公告)日：2008-11-18
申请号：US11450711
申请日：2006-06-09
申请人： Swarup Bhunia , Nilanjan Banerjee , Hamid Mahmoodi , Qikai Chen , Kaushik Roy
发明人： Swarup Bhunia , Nilanjan Banerjee , Hamid Mahmoodi , Qikai Chen , Kaushik Roy
IPC分类号： G06F17/50
CPC分类号： H03K19/0016
摘要： A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.
摘要翻译： 一种逻辑合成方法，用于将电源门控应用于其主动操作模式中的通用逻辑电路的空闲部分，以减少功率需求及由此产生的电路。 利用香农膨胀来确定通用逻辑电路的空闲部分和有效部分。
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公开(公告)号：US20110113392A1
公开(公告)日：2011-05-12
申请号：US12942675
申请日：2010-11-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F21/75 , G09C1/00 , H04L2209/16
摘要： One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.
摘要翻译： 一个实施例提供了一种用于保护集成电路芯片设计的方法。 该方法可以包括在存储器中存储包括一组节点的集成电路核心的电路描述，并从该组节点中选择多个修改节点。 可以将顺序结构插入电路描述中以提供修改的电路描述，利用多个修改节点作为输入的顺序结构。 修改后的电路描述可以存储在存储器中。
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7.发明授权Low power scan design and delay fault testing technique using first level supply gating 失效低功耗扫描设计和延时故障测试技术采用一级电源门控公开(公告)号：US07319343B2
公开(公告)日：2008-01-15
申请号：US11099386
申请日：2005-04-05
IPC分类号： H03K19/173 , G01R31/28
CPC分类号： G01R31/31858
摘要： A circuit includes an input block and a combinational logic block. The input block has reconfigurable latches that are connected serially during testing times such that an output of one of the latches is connected to an input of a successive latch. The latches are directly connected to first level gates of the combinational logic block. The combinational logic block contains switches that prevent the propagation of signals through the combinational logic block during testing times other than when a desired vector is loaded into the latches. The switches disconnect the power and/or ground from the first level gates. The switches further connect the outputs of the first level gates to power or ground, depending on the type of transistors used in the first level gates. The switches alternatively delay the output through a pair of inverters and resupply the output to itself if refreshing the output is desired.
摘要翻译： 电路包括输入块和组合逻辑块。 输入块具有可重新配置的锁存器，其在测试时间期间串行连接，使得一个锁存器的输出连接到连续锁存器的输入端。 锁存器直接连接到组合逻辑块的第一级门。 组合逻辑块包含开关，其防止在测试期间通过组合逻辑块传播信号，而不是当期望的矢量被加载到锁存器时。 开关从第一级门断开电源和/或接地。 这些开关根据第一级门中使用的晶体管的类型进一步将第一电平门的输出连接到电源或接地。 交换机通过一对逆变器交替地延迟输出，并且如果需要刷新输出，则将输出再供给到其自身。
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公开(公告)号：US20070242538A1
公开(公告)日：2007-10-18
申请号：US11404667
申请日：2006-04-14
申请人： Qikai Chen , Swarup Bhunia , Hamid Mahmoodi , Kaushik Roy
发明人： Qikai Chen , Swarup Bhunia , Hamid Mahmoodi , Kaushik Roy
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50016
摘要： A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second time instants. If the contents are different from one another, the comparator indicates that a fault has occurred. Test methods are also used to determine if a fault has occurred in a memory cell.
摘要翻译： 用于确定存储器件中的故障的测试电路。 测试电路包括：读取电路，被配置为在第一时刻和第二时刻读取存储器件中的存储单元内容。 测试电路包括比较第一和第二时刻的内容的比较器。 如果内容不同，则比较器指示发生故障。 测试方法也用于确定存储器单元中是否发生故障。
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