公开(公告)号：US09836567B2

公开(公告)日：2017-12-05

申请号：US14424212

申请日：2012-09-14

申请人： Asher Berkovitz ,  Uzi Magini ,  Michael Priel

发明人： Asher Berkovitz ,  Uzi Magini ,  Michael Priel

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5022 ,  G06F17/5081 ,  G06F2217/08 ,  Y02T10/82

摘要： A method and device for simulating a semiconductor IC is provided, which comprises generating a high level description of the IC, generating a low level description of the IC comprising a plurality of instances describing the operation of the IC, conducting a low level function analysis of the IC based on metrics values associated with the instances, and performing a design optimization scheme. The scheme comprises mapping the metric values of instances describing functional units different from standard cells, to standard cells logically connected to said instances, by dividing each of the instance metrics values between a group of standard cells logically connected to the corresponding instance and adding each resulting portion of said instance metric value to the metric value of each of the group of standard cells, respectively.

公开(公告)号：US09607117B2

公开(公告)日：2017-03-28

申请号：US14650319

申请日：2013-01-08

申请人： Asher Berkovitz ,  Michael Priel ,  Sergey Sofer

发明人： Asher Berkovitz ,  Michael Priel ,  Sergey Sofer

IPC分类号： G06F17/50 ,  H03K3/037

CPC分类号： G06F17/5031 ,  G06F17/5059 ,  G06F17/5081 ,  G06F2217/84 ,  H03K3/0375

摘要： A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

公开(公告)号：US20150347655A1

公开(公告)日：2015-12-03

申请号：US14288531

申请日：2014-05-28

申请人： AMIR GRINSHPON ,  OSNAT ARAD ,  ASHER BERKOVITZ

发明人： AMIR GRINSHPON ,  OSNAT ARAD ,  ASHER BERKOVITZ

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

摘要： An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.

摘要翻译： 提供了集成电路设计，计算机程序产品和非暂时有形计算机可读存储介质的分层集成电路设计的设备和方法。 该装置包括用于接收分层集成电路设计的输入，用于选择候选输出引脚的选择器，用于调整分级集成电路设计的克隆器，用于调整分级集成电路设计的重新连接器以及用于输出分级集成电路设计的输出 适应分层电路设计。 可选地，该装置包括定时改进剂。 该装置选择作为具有矛盾的定时违规的至少两个定时路径上的节点的IP块的候选输出引脚。 克隆候选输出引脚，并且至少一个定时路径连接到IP块的一个实例的克隆输出引脚。

公开(公告)号：US09171117B2

公开(公告)日：2015-10-27

申请号：US14003361

申请日：2011-03-28

申请人： Asher Berkovitz ,  Gal Malach ,  Eytan Weisberger

发明人： Asher Berkovitz ,  Gal Malach ,  Eytan Weisberger

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5022

摘要： The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.

摘要翻译： 本发明涉及一种用于对集成电路设计的功率优化的路径进行排序的方法，包括识别集成电路设计的多个路径，每个路径包括电子设备的一个或多个实例，其中为每个实例提供实例功率估计 识别的路径，对于每个所识别的路径，基于路径中的实例的实例功率估计提供至少一个加权功率估计，以及基于所述至少一个加权功率估计提供所述路径的等级。 本发明还涉及相应的计算机程序产品。

公开(公告)号：US20150276869A1

公开(公告)日：2015-10-01

申请号：US14438234

申请日：2012-10-30

申请人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL

发明人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

IPC分类号： G01R31/3177 ,  G01R31/3185

摘要： There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.

摘要翻译： 提供了包括至少一个逻辑路径的集成电路，其包括可操作地耦合到扫描链中以形成至少一个待测扫描链的多个顺序逻辑元件，至少一个IR压降传感器，可操作地耦合到集成电路电源 ，当所感测的电源电压低于第一预定义值时，可操作以输出第一逻辑状态，并且当感测到的电源电压高于第一预定值时输出第二逻辑状态，至少一个存储器缓冲器可操作地耦合到扫描测试数据 负载输入和待测试的至少一个扫描链的扫描测试数据输出，以及当所述至少一个IR下降传感器输出时，控制逻辑可操作以对包含集成电路内的扫描移位操作的门逻辑活动进行单个周期 所述第一逻辑状态并且当所述至少一个IR下降传感器输出所述第二逻辑状态时允许正常的扫描测试流程。 还提供了执行集成电路的高速扫描测试的相关方法。

公开(公告)号：US20150247899A1

公开(公告)日：2015-09-03

申请号：US14431794

申请日：2012-09-27

申请人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL ,  FREESCALE SEMICONDUCTOR, INC.

发明人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

IPC分类号： G01R31/3185

CPC分类号： G01R31/318544 ,  G01R31/318575

摘要： A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.

摘要翻译： 一种方法产生用于测试具有扫描路径的称为DUT的电子设备的扫描模式。 扫描测试器被布置用于执行扫描移位模式和捕获模式。 扫描测试接口具有时钟控制单元，用于根据扫描时钟模式拉伸扫描时钟的移位周期。 该方法确定在扫描移位模式的相应移位周期期间期望导致电源电压超过预定阈值的电压降的至少一个功率偏移周期，并且除了扫描模式之外还产生指示的扫描时钟模式 拉伸动力换档循环。 有利地，可以使用相对高的扫描偏移频率，同时通过扩展相应的功率偏移周期来避免所述电压降的不利影响，从而降低测试时间和产量损失。

公开(公告)号：US09709629B2

公开(公告)日：2017-07-18

申请号：US14758969

申请日：2013-01-08

申请人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

发明人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

IPC分类号： G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318575

摘要： The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains.

公开(公告)号：US09542523B2

公开(公告)日：2017-01-10

申请号：US14424220

申请日：2012-09-14

申请人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

发明人： Michael Priel ,  Asher Berkovitz ,  Slavaf Fleshel ,  Amir Grinshpon ,  Dan Kuzmin ,  Yoav Miller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031

摘要： A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.

摘要翻译： 描述了用于在集成电路（IC）设计中选择用于克隆的数据路径元素的方法和装置。 该方法包括对IC设计中的至少一个数据路径执行定时分析以确定至少一个数据路径的至少一个定时松弛值，计算至少一个注释的延迟值，以克隆至少一个数据中的候选元素 路径，根据至少一个计算出的注释延迟值计算至少一个数据路径的至少一个经修改的松弛值，以及至少部分地基于至少一个修改的松弛值来验证候选元素的克隆。

公开(公告)号：US09235673B2

公开(公告)日：2016-01-12

申请号：US14288531

申请日：2014-05-28

申请人： Amir Grinshpon ,  Osnat Arad ,  Asher Berkovitz

发明人： Amir Grinshpon ,  Osnat Arad ,  Asher Berkovitz

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

摘要： An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.

摘要翻译： 提供了集成电路设计，计算机程序产品和非暂时有形计算机可读存储介质的分层集成电路设计的设备和方法。 该装置包括用于接收分层集成电路设计的输入，用于选择候选输出引脚的选择器，用于调整分级集成电路设计的克隆器，用于调整分级集成电路设计的重新连接器以及用于输出分级集成电路设计的输出 适应分层电路设计。 可选地，该装置包括定时改进剂。 该装置选择作为具有矛盾的定时违规的至少两个定时路径上的节点的IP块的候选输出引脚。 克隆候选输出引脚，并且至少一个定时路径连接到IP块的一个实例的克隆输出引脚。

公开(公告)号：US20150338460A1

公开(公告)日：2015-11-26

申请号：US14758969

申请日：2013-01-08

申请人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL

发明人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL

IPC分类号： G01R31/3177 ,  G01R31/317

CPC分类号： G01R31/3177 ,  G01R31/31727 ,  G01R31/318575

摘要： The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains.

摘要翻译： 本发明提供了一种用于对集成电路的至少两个扫描链进行快速扫描扫描测试的方法，包括迭代地移位用移位时钟定时扫描的第一个扫描链的功能元件的设定值，迭代移位 设置用移位时钟计时的第二扫描链的功能元件的值，在第一个扫描链的第一个扫描链的最后一个移位周期启动以第一个扫描链的功能时钟为时钟的高速扫描测试 扫描链，延迟扫描链中的第二扫描链的最后一个移位周期达预定的时间跨度，在第二个扫描链的最后一个移位周期启动用第二扫描链的功能时钟计时的速度扫描测试 其中一个扫描链，在扫描链的最后一个移位周期之后捕获第一和第二扫描链的功能元件的样本值。