公开(公告)号：US09917581B2

公开(公告)日：2018-03-13

申请号：US14398318

申请日：2012-05-29

申请人： Sergey Sofer ,  Eyal Melamed-Kohen ,  Michael Priel

发明人： Sergey Sofer ,  Eyal Melamed-Kohen ,  Michael Priel

IPC分类号： H03K17/30 ,  H03K17/94 ,  H03K17/0412 ,  H03K17/693

CPC分类号： H03K17/94 ,  H03K17/04123 ,  H03K17/302 ,  H03K17/693 ,  Y10T307/344 ,  Y10T307/549

摘要： An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described.

公开(公告)号：US09842066B2

公开(公告)日：2017-12-12

申请号：US14398876

申请日：2012-05-31

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G06F13/10 ,  G11C7/04 ,  G11C7/10 ,  G06F1/14

CPC分类号： G06F13/10 ,  G06F1/14 ,  G11C7/04 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1087 ,  G11C7/1096

摘要： An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

公开(公告)号：US09607117B2

公开(公告)日：2017-03-28

申请号：US14650319

申请日：2013-01-08

申请人： Asher Berkovitz ,  Michael Priel ,  Sergey Sofer

发明人： Asher Berkovitz ,  Michael Priel ,  Sergey Sofer

IPC分类号： G06F17/50 ,  H03K3/037

CPC分类号： G06F17/5031 ,  G06F17/5059 ,  G06F17/5081 ,  G06F2217/84 ,  H03K3/0375

摘要： A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

公开(公告)号：US20160183033A1

公开(公告)日：2016-06-23

申请号：US14580729

申请日：2014-12-23

申请人： OLEG POGORELIK ,  SHAHAR PORAT ,  GENNADY GOLTMAN ,  SERGEY SOFER ,  ALEX NAYSHTUT ,  AVISHAY SHARAGA ,  MIGUEL BALLESTEROS

发明人： OLEG POGORELIK ,  SHAHAR PORAT ,  GENNADY GOLTMAN ,  SERGEY SOFER ,  ALEX NAYSHTUT ,  AVISHAY SHARAGA ,  MIGUEL BALLESTEROS

IPC分类号： H04W4/00 ,  H04W12/04

CPC分类号： H04W12/04 ,  H04L63/067 ,  H04L67/125 ,  H04L67/28 ,  H04L67/34 ,  H04W4/80

摘要： Described herein are architectures, platforms and methods for offloading process or application from a near field communication (NFC) master device for proxy delegation to a proxy NFC device.

摘要翻译： 这里描述了用于从用于代理委托给代理NFC设备的近场通信（NFC）主设备卸载进程或应用程序的架构，平台和方法。

公开(公告)号：US09263433B2

公开(公告)日：2016-02-16

申请号：US14359695

申请日：2011-11-22

申请人： Sergey Sofer ,  Valery Neiman ,  Michael Priel

发明人： Sergey Sofer ,  Valery Neiman ,  Michael Priel

IPC分类号： H02H3/22 ,  H01L27/02 ,  H01L23/04 ,  H01L23/50 ,  H02H9/04 ,  H05K1/02

CPC分类号： H01L27/0285 ,  H01L23/04 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  H05K1/0259 ,  H01L2924/00

摘要： An integrated circuit comprising a power supply node, a ground node and a gated domain coupled between the power node and the ground node. A Charged Device Model electrostatic discharge protection module is provided for shunting electrical energy of a CDM ESD event away from the gated domain. A gating switch makes an electrical connection in a connected state between the gated domain and at least one of the power node and the ground node. ESD gating control circuitry is coupled to the CDM ESD protection module and controls shunting of energy away from the gated domain by the CDM ESD protection module, thereby avoiding the energy flowing through the gated domain. The ESD gating control circuitry inhibits actuation of the CDM ESD protection module to prevent response to CDM ESD events when the gating domain is powered-up.

摘要翻译： 一种集成电路，包括电源节点，接地节点和耦合在功率节点和接地节点之间的选通域。 带电装置型号的静电放电保护模块用于将CDM ESD事件的电能与门控域分开。 选通开关在门控域与功率节点和接地节点中的至少一个之间的连接状态下进行电连接。 ESD选通控制电路耦合到CDM ESD保护模块，并通过CDM ESD保护模块控制远离门控域的能量分流，从而避免流过门控域的能量。 ESD选通控制电路禁止CDM ESD保护模块的启动，以防止在门控域加电时对CDM ESD事件的响应。

公开(公告)号：US20150276870A1

公开(公告)日：2015-10-01

申请号：US14438237

申请日：2012-11-07

申请人： Michael PRIEL ,  Dan KUZMIN ,  Sergey SOFER

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G01R31/3177

CPC分类号： G01R31/3177 ,  G06F1/3287 ,  G11C29/32 ,  Y02D10/171 ,  Y02D50/20

摘要： A method of performing state retention, for example during power gating, for at least one functional block within an integrated circuit device. The method comprises enabling at least one scan chain within the at least one functional block, scanning out a set of scan chain values from the at least one scan chain, a subset of the set of scan chain values comprising validation values, and writing the set of scan chain values to at least one memory element. The method further comprises retrieving the set of scan chain values from the at least one memory element, and validating the validation values within the retrieved set of scan chain values.

摘要翻译： 一种在集成电路装置内的至少一个功能块执行状态保持的方法，例如在功率选通期间。 该方法包括启用至少一个功能块内的至少一个扫描链，从至少一个扫描链扫描一组扫描链值，包括验证值的扫描链值集合的子集，以及写入该集合 的扫描链值至少一个存储元件。 该方法还包括从至少一个存储器元件检索该组扫描链值，以及验证所检索的扫描链值集合内的验证值。

公开(公告)号：US09075421B2

公开(公告)日：2015-07-07

申请号：US14116785

申请日：2011-05-27

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G05F1/46 ,  G06F1/26

CPC分类号： G05F1/46 ,  G06F1/26

摘要： An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

摘要翻译： 一种集成电路装置，包括至少一个电压供应模块，其布置成在其输入处接收至少一个控制信号，并在其输出端提供根据所接收的至少一个控制信号的电压信号，以及至少一个控制模块 包括在所述至少一个电压供应模块的输出和所述至少一个电压供应模块的输入之间的至少一个反馈环路，并被布置成至少部分地基于所述电压的电压电平来产生所述至少一个控制信号 信号由所述至少一个电压供应模块输出。 所述至少一个控制模块还被布置成在其输入处接收至少一个电压供应模块的输出处的负载电流的至少一个瞬时指示，并且向提供给所述至少一个电压供应模块的至少一个控制信号施加补偿 至少一个电压供应模块至少部分地基于接收到的负载电流的至少一个指示。

公开(公告)号：US20150181435A1

公开(公告)日：2015-06-25

申请号：US14135875

申请日：2013-12-20

申请人： Sergey Sofer ,  Shahar Wolf

发明人： Sergey Sofer ,  Shahar Wolf

IPC分类号： H04W12/12 ,  H04B5/00

CPC分类号： H04W12/12 ,  H04B5/0031 ,  H04B5/0081 ,  H04W4/80

摘要： Systems and methods to secure near field communications (NFC) are disclosed. An NFC polling device may detect a change in voltage when attempting to communicate with another NFC device and based at least in part on the magnitude of the change in voltage if there is an attempted hacking and/or snooping event. The NFC polling device may further identify the number of modulation voltage levels detected and determine if there is an attempted hacking event based on the number of modulation voltage levels detected.

摘要翻译： 公开了用于保护近场通信（NFC）的系统和方法。 当尝试与另一个NFC设备进行通信时，NFC轮询设备可以检测电压的变化，并且至少部分地基于如果存在尝试的黑客和/或窥探事件的电压变化的大小。 NFC轮询设备还可以识别检测到的调制电压电平的数量，并且基于检测到的调制电压电平的数量来确定是否存在尝试的黑客事件。

公开(公告)号：US20150084417A1

公开(公告)日：2015-03-26

申请号：US14398318

申请日：2012-05-29

申请人： Sergey Sofer ,  Eyal Melamed-Kohen ,  Michael Priel

发明人： Sergey Sofer ,  Eyal Melamed-Kohen ,  Michael Priel

IPC分类号： H03K17/94 ,  H03K17/30

CPC分类号： H03K17/94 ,  H03K17/04123 ,  H03K17/302 ,  H03K17/693 ,  Y10T307/344 ,  Y10T307/549

摘要： An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described.

摘要翻译： 提出了一种包括可连接或连接在第一电压源和负载之间的第一电源开关的电子设备。 响应于断电请求，第一电源开关响应于上电请求和非导通状态而呈现导通状态，用于对负载进行供电和断电，使得第一电源开关上的电压趋向于 当第一电源开关处于导通状态时，当第一电源开关处于非导通状态时为正高电平，并且在第一电源开关处于导通状态时为正高电平。 该装置还包括可连接或连接在第二电压源和负载之间的第二电源开关。 当第一功率开关上的电压低于低于高电平的限定的关断阈值时，第二电源开关响应于电源接通请求而呈现导通状态和非导通状态。 因此，第二电压源因此辅助第一电压源来加载负载。 还描述了操作电子设备的方法。

公开(公告)号：US20140085758A1

公开(公告)日：2014-03-27

申请号：US14115210

申请日：2011-05-27

申请人： Sergey Sofer ,  Moty Groissman ,  Valery Neiman

发明人： Sergey Sofer ,  Moty Groissman ,  Valery Neiman

IPC分类号： H01L23/34 ,  H01L23/60

CPC分类号： H01L23/34 ,  H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device comprising at least one electrostatic discharge (ESD) clamp device. The at least one ESD clamp device comprises a first channel input, a second channel input, and a control input arranged to receive a control signal. The at least one ESD clamp device is arranged to selectively operate in a conductive state in which the at least one ESD clamp device permits current to flow between the first and second channel inputs thereof based at least partly on the received control signal. The integrated circuit device further comprises at least one biasing module. The at least one biasing module comprises at least one output operably coupled to the control input of the at least one ESD clamp device and at least one input arranged to receive a thermal regulation signal. The at least one biasing module being arranged to apply a bias to the control signal for the at least one ESD clamp device based at least partly on the received thermal regulation signal.

摘要翻译： 一种包括至少一个静电放电（ESD）钳位装置的集成电路装置。 所述至少一个ESD钳位装置包括第一通道输入，第二通道输入和布置成接收控制信号的控制输入。 所述至少一个ESD钳位装置被布置成选择性地在导电状态下工作，其中所述至少一个ESD钳位装置允许电流至少部分地基于所接收的控制信号而在其第一和第二通道输入之间流动。 集成电路装置还包括至少一个偏置模块。 所述至少一个偏置模块包括可操作地耦合到所述至少一个ESD钳位装置的控制输入的至少一个输出和布置成接收热调节信号的至少一个输入。 所述至少一个偏置模块被布置成至少部分地基于所接收的热调节信号，将至少一个ESD钳位装置的控制信号施加偏压。