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公开(公告)号：US08581658B2
公开(公告)日：2013-11-12
申请号：US13082918
申请日：2011-04-08
摘要： A charge pump circuit comprises a first node, a second node, and at least one capacitance stage coupled between the first node and the second node. Capacitance stages of the at least one capacitance stage are coupled in series. A capacitance stage of the at least one capacitance stage includes a capacitive device and a voltage limiter coupled in parallel with the capacitor. The voltage limiter is configured to limit a voltage dropped across the capacitor. The capacitive device and the voltage limiter are configured such that a first current flowing through a first branch having the voltage limiter is more than a second current flowing through a second branch having the capacitive device.
摘要翻译： 电荷泵电路包括第一节点，第二节点和耦合在第一节点和第二节点之间的至少一个电容级。 至少一个电容级的电容级串联耦合。 至少一个电容级的电容级包括电容器件和与电容器并联耦合的限压器。 电压限制器被配置为限制电容器下降的电压。 电容性器件和限压器被配置为使流过具有限压器的第一支路的第一电流大于流过具有电容器件的第二支路的第二电流。
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公开(公告)号：US08681576B2
公开(公告)日：2014-03-25
申请号：US13118956
申请日：2011-05-31
IPC分类号： G11C7/00
CPC分类号： G11C11/4094
摘要： A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line.
摘要翻译： 电路包括一组预充电和均衡装置，控制信号线和字线。 该组预充电和均衡装置被配置为对一对数据线进行预充电和均衡。 控制信号线被配置为控制预充电和均衡装置。 字线被配置为将存储器单元电耦合到该对数据线的数据线。 提供给控制信号线的第一电压值来自不同于产生字线的第二电压值的第二电压源的第一电压源。
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公开(公告)号：US08619462B2
公开(公告)日：2013-12-31
申请号：US13543495
申请日：2012-07-06
CPC分类号： G11C11/4091 , Y10T307/50
摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
摘要翻译： 一些实施例涉及包括存储器单元，第一数据线，第二数据线，耦合到第一数据线和第二数据线的感测电路的电路，经由至少三个相应的选择性地耦合到至少三个电压源的节点 开关，第四开关和第五开关。 第一电压源被配置为经由第一开关向节点提供保持电压。 第二电压源被配置为经由第二开关向节点提供接地参考电压，并且第三电压源被配置为经由第三开关向节点提供参考电压。 第四开关和第五开关被配置为接收相应的第一控制信号和第二控制信号，并将节点处的电压传递到相应的第一数据线和第二数据线。
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4.发明授权公开(公告)号：US08619483B2
公开(公告)日：2013-12-31
申请号：US12831385
申请日：2010-07-07
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to a first voltage that is substantially equal to and higher than a threshold voltage (Vt) of a first transistor of the sense amplifier.
摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和位线耦合。 读出放大器与位线耦合。 读出放大器能够将位线预充电到基本上等于并高于读出放大器的第一晶体管的阈值电压（Vt）的第一电压。
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公开(公告)号：US08238141B2
公开(公告)日：2012-08-07
申请号：US12852638
申请日：2010-08-09
CPC分类号： G11C11/4091 , Y10T307/50
摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.
摘要翻译： 一些实施例涉及包括存储器单元，第一数据线，第二数据线，耦合到第一数据线和第二数据线的感测电路的电路，经由至少三个相应的选择性地耦合到至少三个电压源的节点 开关，第四开关和第五开关。 第一电压源被配置为经由第一开关向节点提供保持电压。 第二电压源被配置为经由第二开关向节点提供接地参考电压，并且第三电压源被配置为经由第三开关向节点提供参考电压。 第四开关和第五开关被配置为接收相应的第一控制信号和第二控制信号，并将节点处的电压传递到相应的第一数据线和第二数据线。
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公开(公告)号：US07429885B2
公开(公告)日：2008-09-30
申请号：US10556113
申请日：2004-08-07
CPC分类号： H03K19/00346 , H03K5/08 , H04L25/085
摘要： A clamper circuit for receiving an input signal from a victim wire, the clamper circuit being capable of receiving aggressor signals from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire and an output signal being selectively enabled based on the logic states of the input signal and the aggressor signals, the clamper circuit also being capable of accelerating the switching of the victim wire when an opposite transition occurs on the aggressors and victim wire at the same time, so as to thereby reduce worst case delay and improve the signal integrity.
摘要翻译： 用于从受害线接收输入信号的钳位电路，钳位电路能够接收来自侵扰线的侵扰信号，侵略线是潜在地在受害线上诱发串扰的信号线，以及基于有选择地启用的输出信号 在输入信号和侵略者信号的逻辑状态下，当在侵略者和受害线同时发生相反的转变时，钳位电路还能够加速受害线的切换，从而减少最坏情况 延迟和提高信号完整性。
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公开(公告)号：US20050257947A1
公开(公告)日：2005-11-24
申请号：US10519767
申请日：2003-06-17
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , H01L27/118 , H03K19/177 , H01B7/00
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/118
摘要： An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid possible routing conflicts around the edges of the integrated circuit (300), which can be introduced by the use of a single type of an asymmetric building block, the integrated circuit (300) is extended with routing cells (200) that provide routing at the edges of the grid that are uncovered by the routing networks of the building blocks (100a-i). The routing cells (200) and the switch cell (250) are combined with a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Consequently, an integrated circuit (300) is presented that comprises only a single type of building block (100a-i) but still has a fully symmetric routing architecture.
摘要翻译： 集成电路（300）具有由基本上相同的构建块（100a-i）形成的规则网格。 为了避免可以通过使用单一类型的非对称构建块引入的集成电路（300）的边缘周围的可能的路由冲突，集成电路（300）被扩展，路由单元（200）提供路由 在由所述构建块（100a）的路由网络未覆盖的所述网格的边缘处。 路由单元（200）和交换单元（250）与第一路由结构（330）和第二路由结构（340）组合以形成围绕集成电路（300）的网格的路由网络（280）。 因此，提出了仅包括单一类型的构建块（100a-i）但仍具有完全对称的路由架构的集成电路（300）。
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公开(公告)号：US07605740B2
公开(公告)日：2009-10-20
申请号：US12097040
申请日：2006-12-08
申请人： Marcel Pelgrom , Atul Katoch , Maarten Vertregt
发明人： Marcel Pelgrom , Atul Katoch , Maarten Vertregt
IPC分类号： H03M1/36
CPC分类号： H03M1/0673 , H03M1/365
摘要： A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.
摘要翻译： 闪存模数转换器包括由参考电压源供电的电阻串，用于提供一组等距参考电压，以及一组比较器，用于将模拟输入信号与参考电压进行比较。 一组开关被布置和控制以执行用于减轻组件之间的错配的影响的算法。 开关布置在参考电压源和电阻串之间，从而避免了比较器的参考输入中的开关。 电阻串优选为圆形。 转换器可以处理差分信号。
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公开(公告)号：US20060244481A1
公开(公告)日：2006-11-02
申请号：US10558145
申请日：2004-05-17
申请人： Atul Katoch , Manish Garg , Evert Seevinck , Hendricus Veendrick
发明人： Atul Katoch , Manish Garg , Evert Seevinck , Hendricus Veendrick
IPC分类号： H03K19/003
CPC分类号： G06F13/4072
摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.
摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。
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公开(公告)号：US09019782B2
公开(公告)日：2015-04-28
申请号：US13551387
申请日：2012-07-17
申请人： Atul Katoch
发明人： Atul Katoch
IPC分类号： G11C7/00 , G11C11/4074 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4074 , G11C11/4091 , G11C11/4097
摘要： A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.
摘要翻译： 存储器宏包括多个存储单元，多个第一放大电路，第一驱动电路和第一电平移位器。 多个存储单元被布置成第一方向的组和第二方向的组。 每个放大电路经由第一数据线耦合到布置在第一组第一组中的多个第一存储单元。 第一驱动电路被配置为驱动多个第一放大电路。 第一电平移位器被配置为将在第一功率域中操作的输入信号电平移位到在第二功率域中操作的输出信号。 第一电平移位器的输出信号由第一驱动电路使用。 第一驱动电路和放大电路的读出放大器在第二功率域中工作。
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