公开(公告)号：US06356796B1

公开(公告)日：2002-03-12

申请号：US09216752

申请日：1998-12-17

申请人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

发明人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

IPC分类号： G06F1900

CPC分类号： G06F17/5063 ,  G06F17/5036 ,  G06F17/5045

摘要： A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow. Additionally, this invention may be implemented in a set of commercially available computer software programs.

摘要翻译： 用于开发集成电路（IC）的语言控制设计流程，允许用户对IC设计进行特征，合成，模拟和分析。 语言控制设计流程提供了专门的功能，可实现快速设计开发和知识产权（IP）重用。 该语言提供了在表征，综合，仿真和分析期间捕获设计人员对这些组件特有的设计组件和设计过程的了解。 本发明的一个特征是能够将组件特定知识与用于分析的工具分开设计或设计。 这将导致整体工具集的可扩展性，简单性，准确性和性能的好处。 还提供了一种机制，其中设计过程可以通过语言控制的设计流程完全自动化，该流程可以利用设计，设计组件以及设计过程流程中可用的信息。 另外，本发明可以在一组市售的计算机软件程序中实现。

公开(公告)号：US4464771A

公开(公告)日：1984-08-07

申请号：US364956

申请日：1982-04-02

申请人： Bendt H. Sorensen

发明人： Bendt H. Sorensen

IPC分类号： H04L7/033 ,  H04L7/02

CPC分类号： H04L7/033

摘要： The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another.A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited.The invention is particularly applicable to teletext receivers.

摘要翻译： 所描述的本发明涉及一种用于将振荡器同步到非归零数据信号的锁相环电路装置，其中从一个电位电平到另一个电位电平的转换代表从一个二进制值到另一个二进制值的数据转换。 通过可控振荡器提供本地时钟信号，相位比较器将数据和时钟信号的相位彼此进行比较。 根据数据相位与时钟信号的相位相反的量，通过控制信号来调整振荡器的频率，反之亦然。 在其中时钟信号的相位导致数据的相位并且其中没有数据转换发生的时钟信号的任何周期中，禁止向振荡器施加控制信号。 本发明特别适用于图文电视接收机。