公开(公告)号：US6101323A

公开(公告)日：2000-08-08

申请号：US116010

申请日：1998-07-15

申请人： Thomas L. Quarles ,  S. Peter Liebmann ,  Leslie D. Spruiell

发明人： Thomas L. Quarles ,  S. Peter Liebmann ,  Leslie D. Spruiell

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.

公开(公告)号：US06374390B1

公开(公告)日：2002-04-16

申请号：US09461246

申请日：1999-12-15

申请人： Thomas L. Quarles ,  S. Peter Liebmann ,  Leslie D. Spruiell

发明人： Thomas L. Quarles ,  S. Peter Liebmann ,  Leslie D. Spruiell

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.

摘要翻译： 一种用于减少表示电路的矩阵的评估时间的装置。 使用非阻塞写入技术将电路中每个电路元件的电导值写入相应的模型。 矩阵由减小的存储器结构表示，其中每个矩阵节点由矩阵元素结构表示，该矩阵元素结构具有至少一个指向包含在对有助于矩阵节点的值的电路分量的模型结构中的电导值的指针。 然后处理一组矩阵的行或列以独立地计算最终矩阵节点值。

公开(公告)号：US07076415B1

公开(公告)日：2006-07-11

申请号：US09560844

申请日：2000-04-28

申请人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis ,  Leslie D. Spruiell ,  Robert W. McGuffin ,  Bent H. Sorensen

发明人： Michael J. Demler ,  Stephen Lim ,  Geoffrey Ellis ,  Leslie D. Spruiell ,  Robert W. McGuffin ,  Bent H. Sorensen

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F2217/86

摘要： Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.

摘要翻译： 利用优化器进行电路合成，所述优化器基于期望的性能特征和先前合成的电路的性能特征/设计参数来选择电路的合成模型的设计参数。 每个合成电路的性能特征和设计参数与正在合成的电路的合成模型相结合。 综合计划确定了如何执行设计参数优化选择，如何设置测试台以及如何执行仿真的综合模型和具体说明。

公开(公告)号：US06356796B1

公开(公告)日：2002-03-12

申请号：US09216752

申请日：1998-12-17

申请人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

发明人： Leslie D. Spruiell ,  Robert W. McGuffin ,  Bendt H. Sorensen ,  Michael J. Demler

IPC分类号： G06F1900

CPC分类号： G06F17/5063 ,  G06F17/5036 ,  G06F17/5045

摘要： A Language Controlled Design Flow for the development of integrated circuits (IC) that allows users to Characterize, Synthesize, Simulate, and Analyze IC designs. The Language Controlled Design Flow provides specialized features that enable rapid design development and Intellectual Property (IP) reuse. The language provides the ability to capture a designer's knowledge about the Design Components and Design Processes unique to those components during characterization, synthesis, simulation, and analysis. A feature of this invention is the ability to separate design or design component specific knowledge from the tools used for analysis. This leads to benefits in extensibility, simplicity, accuracy, and performance of the overall tool set. Also provided is a mechanism in which the design process can be fully automated with a Language Controlled Design Flow that can take advantage of the information available in the design, in the design components, and in the design process flow. Additionally, this invention may be implemented in a set of commercially available computer software programs.

摘要翻译： 用于开发集成电路（IC）的语言控制设计流程，允许用户对IC设计进行特征，合成，模拟和分析。 语言控制设计流程提供了专门的功能，可实现快速设计开发和知识产权（IP）重用。 该语言提供了在表征，综合，仿真和分析期间捕获设计人员对这些组件特有的设计组件和设计过程的了解。 本发明的一个特征是能够将组件特定知识与用于分析的工具分开设计或设计。 这将导致整体工具集的可扩展性，简单性，准确性和性能的好处。 还提供了一种机制，其中设计过程可以通过语言控制的设计流程完全自动化，该流程可以利用设计，设计组件以及设计过程流程中可用的信息。 另外，本发明可以在一组市售的计算机软件程序中实现。