公开(公告)号：US09406272B2

公开(公告)日：2016-08-02

申请号：US13301637

申请日：2011-11-21

申请人： Jae-Hoon Lee ,  Bon-Yong Koo ,  Seung-Hwan Moon ,  Won-Hee Lee

发明人： Jae-Hoon Lee ,  Bon-Yong Koo ,  Seung-Hwan Moon ,  Won-Hee Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0283 ,  G09G2310/0286

摘要： A gate driving circuit includes a shift register and a vertical start line. The shift register includes first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage and at least one forward dummy stage adjacent to the N-th circuit stage (N is a natural number). The vertical start line is electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction and transfers a vertical start signal to the first or N-th circuit stage.

摘要翻译： 栅极驱动电路包括移位寄存器和垂直起始线。 移位寄存器包括分别向第一至第N条栅极线分别提供第一至第N栅极导通信号的第一至第N电路级，与第一电路级相邻的至少一个反虚拟级和至少一个向前 与第N个电路级相邻的虚拟级（N为自然数）。 垂直起始线根据扫描方向电连接到第一电路级或第N电路级，并将垂直启动信号传送到第一或第N电路级。

公开(公告)号：US09024858B2

公开(公告)日：2015-05-05

申请号：US13442583

申请日：2012-04-09

申请人： Bon-Yong Koo ,  Beom Jun Kim ,  Ho Kyoon Kwon

发明人： Bon-Yong Koo ,  Beom Jun Kim ,  Ho Kyoon Kwon

IPC分类号： G09G3/36 ,  G11C19/28 ,  G11C19/00

CPC分类号： G09G3/36 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2320/0209 ,  G11C19/28

摘要： The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.

摘要翻译： 本发明将将扫描开始信号提供给栅极驱动器的线分成两条线，以避免与时钟信号线重叠。 以这种方式，时钟信号不被干扰延迟，并且栅极驱动裕度可以不间断地继续，从而均匀地输出栅极导通电压。 特别地，如果时钟信号线连接到栅极驱动器中的所有级并且时钟信号线与扫描起始信号线重叠，则在图像上出现不好看的水平频带，并行栅极线产生非常大的寄生电容。 相反，本公开的栅极驱动器包括不与扫描起始信号线重叠的时钟信号线。 作为益处，导致水平条带的干扰被最小化，并且功耗可以降低大约10％。

公开(公告)号：US08947409B2

公开(公告)日：2015-02-03

申请号：US12873923

申请日：2010-09-01

申请人： Bon-Yong Koo

发明人： Bon-Yong Koo

IPC分类号： G06F3/038 ,  G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2300/043 ,  G09G2320/0223 ,  G09G2320/041

摘要： A display panel has an amorphous silicon gate driver. A variable capacitor is formed at one end of a gate line to prevent the deterioration of display quality due to high temperature noise. A predetermined level of capacitance is provided to the variable capacitor to the reduce ripple of gate voltage and eliminate the high temperature noise.

摘要翻译： 显示面板具有非晶硅栅极驱动器。 在栅极线的一端形成可变电容器，以防止由于高温噪声导致的显示质量的劣化。 向可变电容器提供预定的电容电平以减小栅极电压的纹波并消除高温噪声。

公开(公告)号：US08659588B2

公开(公告)日：2014-02-25

申请号：US13111065

申请日：2011-05-19

申请人： Bon-Yong Koo

发明人： Bon-Yong Koo

IPC分类号： G06F3/038

CPC分类号： G09G3/3233 ,  G02F1/13454 ,  G09G3/3266 ,  G09G2300/0852 ,  G09G2310/0286 ,  G09G2320/045

摘要： A display substrate includes a base substrate including a display area and a peripheral area, a pixel disposed on the display area, wherein the pixel includes; a pixel transistor connected to a gate line and a data line which cross each other, and a pixel electrode connected to the pixel transistor and the pixel electrode, and a gate driving circuit disposed on the peripheral area, wherein the gate driving circuit outputs a gate signal to the gate line and comprises a plurality of stages, an n-th stage of the gate driving circuit including a plurality of circuit transistors and a boosting capacitor including a first capacitor and a second capacitor, the plurality of circuit transistors and the first capacitor being disposed on a first area and the second capacitor being disposed on a second area of the peripheral area positioned between the first area and the display area.

摘要翻译： 显示基板包括：基板，包括显示区域和外围区域;设置在所述显示区域上的像素，所述像素包括： 连接到栅极线的像素晶体和彼此交叉的数据线，以及连接到像素晶体管和像素电极的像素电极，以及设置在周边区域上的栅极驱动电路，其中栅极驱动电路输出栅极 信号到栅极线并且包括多个级，栅极驱动电路的第n级包括多个电路晶体管和包括第一电容器和第二电容器的升压电容器，所述多个电路晶体管和第一电容器 设置在第一区域上，第二电容器设置在位于第一区域和显示区域之间的外围区域的第二区域上。

公开(公告)号：US20130170151A1

公开(公告)日：2013-07-04

申请号：US13524516

申请日：2012-06-15

申请人： Chong-Guk LEE ,  Sung-Dong PARK ,  Seok-Hyun JUNG ,  Bon-Yong KOO ,  Joo-Yeon WON

发明人： Chong-Guk LEE ,  Sung-Dong PARK ,  Seok-Hyun JUNG ,  Bon-Yong KOO ,  Joo-Yeon WON

IPC分类号： H05K7/00 ,  H05K13/04

CPC分类号： G02F1/13452 ,  G02F1/13454 ,  G09G3/006 ,  G09G2300/0408 ,  G09G2330/12 ,  Y10T29/49002

摘要： A display substrate includes a circuit mounted part that has a driving IC mounted thereon. The circuit mounted part includes an input pad part connected to an input terminal of the driving IC and an output pad part connected to an output terminal of the driving IC. A flexible pad part connected to a terminal of a FPCB includes a driving pad part to receive a drive signal of the driving IC. A driving line part is connected to the driving pad part to be extended along a length direction of the circuit mounted part within the circuit mounted part. Connection lines are extended from the driving line part disposed within the circuit mounted part toward the output pad part. The connection lines are partially removed in a trimming area defined between the driving line and the output pad part.

摘要翻译： 显示基板包括安装有驱动IC的电路安装部。 电路安装部件包括连接到驱动IC的输入端子的输入焊盘部分和连接到驱动IC的输出端子的输出焊盘部分。 连接到FPCB的端子的柔性焊盘部分包括用于接收驱动IC的驱动信号的驱动焊盘部分。 驱动线部分连接到驱动焊盘部分，以沿着电路安装部分内的电路安装部分的长度方向延伸。 连接线从布置在电路安装部分内的驱动线部分朝向输出焊盘部分延伸。 连接线在驱动线和输出焊盘部分之间限定的修整区域中部分地移除。

公开(公告)号：US08368074B2

公开(公告)日：2013-02-05

申请号：US12821317

申请日：2010-06-23

申请人： Bon-Yong Koo

发明人： Bon-Yong Koo

IPC分类号： H01L29/04 ,  H01L31/20 ,  H01L31/036 ,  H01L31/0376

CPC分类号： H01L29/786 ,  H01L33/00 ,  Y02E10/50 ,  Y02P70/521

摘要： A display substrate includes a substrate, a pixel electrode and a dummy pattern part. The substrate includes a display area and a peripheral area surrounding the display area. The pixel electrode is disposed in the display area and electrically connected to gate and data lines. The dummy pattern part is disposed in the peripheral area and includes a plurality of first dummy electrodes connected to each other in a network form through connection electrodes and a plurality of second dummy electrodes respectively disposed over the first dummy electrodes.

摘要翻译： 显示基板包括基板，像素电极和虚设图形部分。 基板包括显示区域和围绕显示区域的周边区域。 像素电极设置在显示区域中并电连接到栅极和数据线。 虚设图形部分设置在周边区域中，并且包括通过连接电极和分别设置在第一虚拟电极上的多个第二虚拟电极以网络形式彼此连接的多个第一虚拟电极。

公开(公告)号：US20120293467A1

公开(公告)日：2012-11-22

申请号：US13301637

申请日：2011-11-21

申请人： Jae-Hoon Lee ,  Bon-Yong Koo ,  Seung-Hwan Moon ,  Won-Hee Lee

发明人： Jae-Hoon Lee ,  Bon-Yong Koo ,  Seung-Hwan Moon ,  Won-Hee Lee

IPC分类号： G09G5/00 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0283 ,  G09G2310/0286

摘要： A gate driving circuit includes a shift register and a vertical start line. The shift register includes first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage and at least one forward dummy stage adjacent to the N-th circuit stage (N is a natural number). The vertical start line is electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction and transfers a vertical start signal to the first or N-th circuit stage.

摘要翻译： 栅极驱动电路包括移位寄存器和垂直起始线。 移位寄存器包括分别向第一至第N条栅极线分别提供第一至第N栅极导通信号的第一至第N电路级，与第一电路级相邻的至少一个反虚拟级和至少一个向前 与第N个电路级相邻的虚拟级（N为自然数）。 垂直起始线根据扫描方向电连接到第一电路级或第N电路级，并将垂直启动信号传送到第一或第N电路级。

公开(公告)号：US08232984B2

公开(公告)日：2012-07-31

申请号：US12559893

申请日：2009-09-15

申请人： Yeong-Keun Kwon ,  Yun-Hee Kwak ,  Bae-Heuk Yim ,  Jeong-Il Kim ,  Bon-Yong Koo ,  Mi-Sun Lee

发明人： Yeong-Keun Kwon ,  Yun-Hee Kwak ,  Bae-Heuk Yim ,  Jeong-Il Kim ,  Bon-Yong Koo ,  Mi-Sun Lee

IPC分类号： G06F3/038

CPC分类号： G09G3/006 ,  G09G3/3677 ,  G09G2310/0267 ,  G11C19/184

摘要： The present invention relates to a thin film transistor array panel and a display device including the same. A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a plurality of gate lines; a plurality of pixels respectively connected to the gate lines; a gate driver comprising a plurality of stages connected to each other, the plurality of stages being respectively connected to the plurality of gate lines and applying gate signals to the plurality of gate lines; and a driver inspection unit separated from the gate driver and including at least three inspection stages, wherein each of the at least three inspection stages has a same structure as one of the plurality of stages of the gate driver.

摘要翻译： 薄膜晶体管阵列面板及其显示装置技术领域本发明涉及薄膜晶体管阵列面板及其构成。 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：多条栅极线; 分别连接到所述栅极线的多个像素; 栅极驱动器，其包括彼此连接的多个级，所述多个级分别连接到所述多条栅极线并将栅极信号施加到所述多条栅极线; 以及驱动器检查单元，其与所述门驱动器分离并且包括至少三个检查级，其中所述至少三个检查级中的每一个具有与所述多个级驱动器中的一级相同的结构。

公开(公告)号：US20110186844A1

公开(公告)日：2011-08-04

申请号：US12821317

申请日：2010-06-23

申请人： BON-YONG KOO

发明人： BON-YONG KOO

IPC分类号： H01L33/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/786 ,  H01L33/00 ,  Y02E10/50 ,  Y02P70/521

摘要： A display substrate includes a substrate, a pixel electrode and a dummy pattern part. The substrate includes a display area and a peripheral area surrounding the display area. The pixel electrode is disposed in the display area and electrically connected to gate and data lines. The dummy pattern part is disposed in the peripheral area and includes a plurality of first dummy electrodes connected to each other in a network form through connection electrodes and a plurality of second dummy electrodes respectively disposed over the first dummy electrodes.

摘要翻译： 显示基板包括基板，像素电极和虚设图形部分。 基板包括显示区域和围绕显示区域的周边区域。 像素电极设置在显示区域中并电连接到栅极和数据线。 虚设图形部分设置在周边区域中，并且包括通过连接电极和分别设置在第一虚拟电极上的多个第二虚拟电极以网络形式彼此连接的多个第一虚拟电极。

公开(公告)号：US20100187538A1

公开(公告)日：2010-07-29

申请号：US12496101

申请日：2009-07-01

申请人： Bon-Yong Koo ,  Bae-Heuk Yim

发明人： Bon-Yong Koo ,  Bae-Heuk Yim

IPC分类号： H01L33/00 ,  H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/124

摘要： A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.

摘要翻译： 根据本发明的薄膜晶体管阵列板包括：具有显示区域和周边区域的绝缘基板; 设置在所述显示区域中的多个薄膜晶体管; 连接到所述薄膜晶体管的多个栅极线; 连接到所述薄膜晶体管的多条数据线; 驱动单元，设置在所述绝缘基板的周边区域中，并控制所述薄膜晶体管; 连接在驱动单元和栅极线或数据线之间的多条信号线; 以及与信号线重叠并由透明导电材料制成的虚拟图案。