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公开(公告)号：US20140203956A1
公开(公告)日：2014-07-24
申请号：US14158818
申请日：2014-01-18
申请人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
发明人： Guy Meynants , Bram WOLFS , Jan BOGAERTS
IPC分类号： H03M1/34
摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
摘要翻译： 用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平 模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。 一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。 控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。 输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。
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公开(公告)号：US09041579B2
公开(公告)日：2015-05-26
申请号：US14158818
申请日：2014-01-18
申请人： Guy Meynants , Bram Wolfs , Jan Bogaerts
发明人： Guy Meynants , Bram Wolfs , Jan Bogaerts
摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
摘要翻译： 用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平 模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。 一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。 控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。 输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。
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公开(公告)号：US20120002089A1
公开(公告)日：2012-01-05
申请号：US12977935
申请日：2010-12-23
申请人： Xinyang Wang , Guy Meynants , Bram Wolfs
发明人： Xinyang Wang , Guy Meynants , Bram Wolfs
IPC分类号： H04N5/335
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14641 , H01L27/14656 , H04N5/35572 , H04N5/3742 , H04N5/3745
摘要： A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element to the second charge conversion element via the second transfer gate.
摘要翻译： 像素结构包括用于响应于入射光而产生电荷的光敏元件。 第一传输门连接在光敏元件和第一电荷转换元件之间。 第二传输门连接在光敏元件和第二电荷转换元件之间。 输出级输出与第一充电转换元件的充电有关的第一值，并输出与第二充电转换元件的电荷相关的第二值。 控制器控制像素结构的操作并引起像素结构。 控制器使得像素结构在曝光期间获取感光元件上的电荷; 将在曝光期间中获取的电荷的第一部分经由第一传输门从光敏元件传送到第一电荷转换元件; 并且将在曝光期间获取的电荷的第二部分经由第二传输门从光敏元件传送到第二电荷转换元件。
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公开(公告)号：US09001245B2
公开(公告)日：2015-04-07
申请号：US12977935
申请日：2010-12-23
申请人： Xinyang Wang , Guy Meynants , Bram Wolfs
发明人： Xinyang Wang , Guy Meynants , Bram Wolfs
IPC分类号： H01L27/146 , H04N5/335 , H04N5/374 , H04N5/3745 , H04N5/355
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14641 , H01L27/14656 , H04N5/35572 , H04N5/3742 , H04N5/3745
摘要： A pixel structure comprises a photo-sensitive element for generating charge in response to incident light. A first transfer gate is connected between the photo-sensitive element and a first charge conversion element. A second transfer gate is connected between the photo-sensitive element and a second charge conversion element. An output stage outputs a first value related to charge at the first charge conversion element and outputs a second value related to charge at the second charge conversion element. A controller controls operation of the pixel structures and causes a pixel structure. The controller causes the pixel structure to: acquire charges on the photo-sensitive element during an exposure period; transfer a first portion of the charges acquired during the exposure period from the photo-sensitive element to the first charge conversion element via the first transfer gate; and transfer a second portion of the charges acquired during the exposure period from the photo-sensitive element to the second charge conversion element via the second transfer gate.
摘要翻译： 像素结构包括用于响应于入射光而产生电荷的光敏元件。 第一传输门连接在光敏元件和第一电荷转换元件之间。 第二传输门连接在光敏元件和第二电荷转换元件之间。 输出级输出与第一充电转换元件的充电有关的第一值，并输出与第二充电转换元件的电荷相关的第二值。 控制器控制像素结构的操作并引起像素结构。 控制器使得像素结构在曝光期间获取感光元件上的电荷; 将在曝光期间中获取的电荷的第一部分经由第一传输门从光敏元件传送到第一电荷转换元件; 并且将在曝光期间获取的电荷的第二部分经由第二传输门从光敏元件传送到第二电荷转换元件。
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