公开(公告)号：US08446309B2

公开(公告)日：2013-05-21

申请号：US13038502

申请日：2011-03-02

申请人： Jan Bogaerts

发明人： Jan Bogaerts

IPC分类号： H03M1/56

CPC分类号： H04N5/3575 ,  G06J1/00 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/202 ,  H03M1/56 ,  H04N5/3742 ,  H04N5/3743 ,  H04N5/378

摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

摘要翻译： 模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC 30接收第一模拟信号电平，第二模拟信号电平和斜坡信号。 计数器32可操作以在单个方向上计数。 控制级被布置为使得计数器32能够基于斜坡信号与第一模拟信号和第二模拟信号的比较19。 计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。 计数器32可以加载代表在先前曝光期间累积的曝光量的开始数字值。 描述了减少转换时间的技术。

公开(公告)号：US08253617B2

公开(公告)日：2012-08-28

申请号：US12982027

申请日：2010-12-30

申请人： Jan Bogaerts

发明人： Jan Bogaerts

IPC分类号： H03M1/56

CPC分类号： H04N5/3575 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/203 ,  H03M1/56

摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

摘要翻译： 模数转换器（ADC）产生等于两个模拟信号值之差的输出数字值。 ADC接收第一模拟信号电平，第二模拟信号电平和斜坡信号。 计数器可操作以在单个方向上计数。 控制级被布置成基于斜坡信号与第一模拟信号和第二模拟信号的比较来使得计数器能够使能。 计数器在启用期间累积的数字值形成输出。 ADC可以在斜坡信号的单个周期内执行转换。 该计数器可以加载起始数字值，表示在先前曝光期间累积的曝光量。 描述了减少转换时间的技术。

公开(公告)号：US20120175499A1

公开(公告)日：2012-07-12

申请号：US13344095

申请日：2012-01-05

申请人： Guy Meynants ,  Jan Bogaerts

发明人： Guy Meynants ,  Jan Bogaerts

IPC分类号： H01L27/148 ,  H01L27/144

CPC分类号： H01L27/14612 ,  H04N5/353 ,  H04N5/3559 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/37452

摘要： A pixel includes a photo-sensitive element for generating charges in response to incident radiation. A transfer gate is positioned between the photo-sensitive element and a sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node and an output connected to a sample stage operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

摘要翻译： 像素包括用于响应入射辐射产生电荷的光敏元件。 传输门位于感光元件和感测节点之间，用于控制向感测节点传输电荷。 复位开关连接到感测节点，用于将感测节点复位到预定电压。 第一缓冲放大器具有连接到感测节点的输入端和连接到可操作以对感测节点的值进行采样的采样台的输出。 第二缓冲放大器具有连接到样品台的输入。 控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。 像素阵列同时暴露于辐射。 可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

公开(公告)号：US20110095926A1

公开(公告)日：2011-04-28

申请号：US12981911

申请日：2010-12-30

申请人： Jan BOGAERTS

发明人： Jan BOGAERTS

IPC分类号： H03M1/12

CPC分类号： H04N5/3575 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/203 ,  H03M1/56

摘要： An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

公开(公告)号：US20100148037A1

公开(公告)日：2010-06-17

申请号：US12544755

申请日：2009-08-20

申请人： Jan BOGAERTS ,  Guy MEYNANTS

发明人： Jan BOGAERTS ,  Guy MEYNANTS

IPC分类号： H03K17/78 ,  H03F3/08

CPC分类号： H01L27/14603 ,  H01L27/14621 ,  H01L27/14641 ,  H04N5/347 ,  H04N5/3651 ,  H04N5/367 ,  H04N5/3745

摘要： A pixel array comprises a plurality of photo-sensitive elements arranged in rows and columns and readout circuitry for reading a value of a photo-sensitive element. Shared readout circuitry is provided for a pair of adjacent photo-sensitive elements. Adjacent instances of the shared readout circuitry are staggered with respect to one another. For a layout having shared readout circuitry for a pair of photo-sensitive elements, adjacent instances of the shared readout circuitry are offset by a horizontal distance of one column and a vertical distance of one row of the array. The shared readout circuitry can serve a pair of adjacent photo-sensitive elements in a row or column of the array, or a pair of photo-sensitive elements which are diagonally adjacent in the array. An improved yield and symmetry results from staggering instances of the shared readout circuitry.

摘要翻译： 像素阵列包括以行和列排列的多个光敏元件以及用于读取感光元件的值的读出电路。 为一对相邻的感光元件提供共享读出电路。 共享读出电路的相邻实例相对于彼此交错。 对于具有用于一对光敏元件的共享读出电路的布局，共享读出电路的相邻实例被一列的水平距离和阵列的一行的垂直距离偏移。 共享读出电路可以在阵列的行或列中的一对相邻的光敏元件或在阵列中对角相邻的一对光敏元件。 由共享读出电路的交错实例产生的改善的产量和对称性。

公开(公告)号：US20090256060A1

公开(公告)日：2009-10-15

申请号：US12408975

申请日：2009-03-23

申请人： Guy MEYNANTS ,  Jan Bogaerts

发明人： Guy MEYNANTS ,  Jan Bogaerts

IPC分类号： H01L27/146 ,  H03F3/08

CPC分类号： H01L27/14612 ,  H04N5/353 ,  H04N5/3559 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/37452

摘要： A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

摘要翻译： 像素包括用于响应于入射辐射产生电荷的感光元件和感测节点。 传输门位于感光元件和感测节点之间，用于控制电荷传递到感测节点。 复位开关连接到感测节点，用于将感测节点复位到预定电压。 第一缓冲放大器具有连接到感测节点的输入。 样本级连接到第一缓冲放大器的输出，并且可操作以对感测节点的值进行采样。 第二缓冲放大器具有连接到样品台的输入。 控制电路操作复位开关，并使样品台在感光元件暴露于辐射的同时采样感测节点。 像素阵列同时暴露于辐射。 可以读取第一曝光期间的采样值，同时在第二曝光期间曝光光敏元件。

公开(公告)号：US20110115663A1

公开(公告)日：2011-05-19

申请号：US12696109

申请日：2010-01-29

申请人： Jan Bogaerts

发明人： Jan Bogaerts

IPC分类号： H03M1/34

CPC分类号： H03M1/123 ,  H03M1/56

摘要： An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage.

摘要翻译： 模拟 - 数字转换器产生与两个模拟信号之间的差值相当的输出数字值。 转换器构成一组转换器的一部分。 转换器接收第一模拟信号和第二模拟信号（Vreset，Vsig）和斜坡信号（Vramp）。 一个时钟专用于转换器或一组转换器。 基于斜坡信号与第一模拟信号和第二模拟信号的比较，控制级使第一计数器成为可能。 转换器可以通过至少一个参考信号（Vref1，Vref2）进行校准，这是一组转换器所共有的。 A到D转换可以包括确定从多个信号范围中选择的信号范围的第一A到D转换级和确定M位数字值等效的第二A到D转换级 通过将信号与斜坡信号进行比较来获得第一和第二模拟信号之间的差异，斜坡信号具有由第一模数转换级确定的信号范围。

公开(公告)号：US06690074B1

公开(公告)日：2004-02-10

申请号：US10233894

申请日：2002-09-03

申请人： Bart Dierickx ,  Jan Bogaerts

发明人： Bart Dierickx ,  Jan Bogaerts

IPC分类号： H01L29772

CPC分类号： H01L31/103 ,  H01L23/585 ,  H01L27/14603 ,  H01L29/0646 ,  H01L31/1136 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure is described for reducing radiation induced current flow caused by incident ionizing radiation. The structure comprises a semiconductor substrate; two or more regions of a first conductivity type in the substrate; and a guard ring of a second conductivity type for obstructing radiation induced parasitic current flow between the two or more regions of the first conductivity type. The structure may be used in a pixel, e.g. in a diode or a transistor, for increasing radiation resistance.

摘要翻译： 描述了用于减少由入射电离辐射引起的辐射感应电流的半导体器件结构。 该结构包括半导体衬底; 衬底中具有第一导电类型的两个或更多个区域; 以及用于阻挡第一导电类型的两个或更多个区域之间的辐射诱发的寄生电流的第二导电类型的保护环。 该结构可以用在像素中，例如， 在二极管或晶体管中，用于增加辐射电阻。

公开(公告)号：US09041579B2

公开(公告)日：2015-05-26

申请号：US14158818

申请日：2014-01-18

申请人： Guy Meynants ,  Bram Wolfs ,  Jan Bogaerts

发明人： Guy Meynants ,  Bram Wolfs ,  Jan Bogaerts

IPC分类号： H03M1/12 ,  H03M1/34 ,  H04N5/378 ,  H03M1/56

CPC分类号： H03M1/34 ,  H03M1/123 ,  H03M1/56 ,  H04N5/378

摘要： An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

摘要翻译： 用于产生与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）之间的差相当的输出数字值的模拟 - 数字转换器包括用于接收第一模拟信号电平的至少一个输入端和第二模拟信号电平 模拟信号电平，用于接收斜坡信号的输入端和用于接收至少一个时钟信号的输入端。 一组N个计数器，其中N≥2，被布置成使用相互偏移的N个时钟信号。 控制级被布置成基于斜坡信号与第一模拟信号电平（Vres）和第二模拟信号电平（Vsig）的比较来使N个计数器能够使能。 输出级被布置为输出数字值，该数字值是在它们被使能的时段期间由N个计数器累积的值的函数。

公开(公告)号：US08710419B2

公开(公告)日：2014-04-29

申请号：US13362082

申请日：2012-01-31

申请人： Jan Bogaerts

发明人： Jan Bogaerts

IPC分类号： H01L27/146

CPC分类号： H01L27/14612 ,  H01L27/1461 ,  H04N5/35572 ,  H04N5/37452

摘要： A pixel structure comprises a photo-sensitive element PPD for generating charges in response to light and a charge conversion element FD. A first transfer gate TX is connected between the photo-sensitive element PPD and the charge conversion element. A charge storage element PG is connected to the photo-sensitive element PPD. The charge storage element PG has a higher charge storage density than the photo-sensitive element PPD. The charge storage element PG is located on the photo-sensitive element PPD side of the first transfer gate TX and is arranged to collect charges generated by the photo-sensitive element PPD during an integration period. The charge storage element can be a photo gate, photodiode or capacitor. Arrangements are provided with, and without, a potential barrier between the photo-sensitive element PPD and the charge storage element PG.

摘要翻译： 像素结构包括用于响应光产生电荷的光敏元件PPD和电荷转换元件FD。 第一传输门TX连接在感光元件PPD和电荷转换元件之间。 电荷存储元件PG连接到感光元件PPD。 电荷存储元件PG具有比感光元件PPD更高的电荷存储密度。 电荷存储元件PG位于第一传输门TX的感光元件PPD侧，并且被布置成在积分期间收集由感光元件PPD产生的电荷。 电荷存储元件可以是光栅，光电二极管或电容器。 在感光元件PPD和电荷存储元件PG之间提供并且不存在势垒的布置。