公开(公告)号：US5781032A

公开(公告)日：1998-07-14

申请号：US707839

申请日：1996-09-09

申请人： Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P.N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K7/38 ,  H03K19/21

CPC分类号： H03K19/1778 ,  H03K19/17728

摘要： A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

摘要翻译： 可编程逻辑单元具有四个单元输入节点和多个组合逻辑电路。 提供四个逆变器电路用于可编程地反相各个输入逻辑信号，每个反相器电路具有连接到各个单元输入节点的反相器输入节点，用于从其接收其相应的输入逻辑信号。 每个逆变器可编程为第一状态，其中表示输入逻辑信号的补码的逻辑信号被提供给逆变器输出节点，并且第二状态，其中表示输入逻辑信号的非补码的逻辑信号被提供给 逆变器输出节点。 逆变器电路在第一和第二状态下缓冲它们的输入逻辑信号。 多个组合逻辑电路的第一逻辑门具有第一和第二输入，每个连接到四个反相器电路中的两个中的一个的相应输出节点，第二逻辑门具有第一和第二输入，每个连接到相应的输出节点 的四个逆变器电路中的另外两个之一。 逆变器电路可以被实现为XNOR门。

公开(公告)号：US5748009A

公开(公告)日：1998-05-05

申请号：US707840

申请日：1996-09-09

申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 优选的编程方法利用用户编程的SRAM存储单元。

公开(公告)号：US5692147A

公开(公告)日：1997-11-25

申请号：US488314

申请日：1995-06-07

申请人： Wendell Ray Larsen ,  Frank Ray Keyser ,  Brian A. Worth

发明人： Wendell Ray Larsen ,  Frank Ray Keyser ,  Brian A. Worth

IPC分类号： H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H03K19/177 ,  G06F12/06

CPC分类号： H03K19/17736 ,  H03K19/17704

摘要： A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.

摘要翻译： 现场可编程门阵列具有可针对x，y二维阵列的每个x和y维度寻址的多个可编程资源。 存储器装置提供存储用于配置现场可编程门阵列的相关可编程资源的配置数据的多个存储器单元。 控制器利用N位地址寻址存储器设备，以检索给定的配置数据。 地址解码器和定序器将N位地址划分为第一，第二和第三部分，并且根据第二部分可互换地采用第一和第三部分，用于寻址用于选择的多个可编程资源的各自的x和y维度 根据检索到的配置数据来配置的相关联的可编程资源。

公开(公告)号：US5717346A

公开(公告)日：1998-02-10

申请号：US709074

申请日：1996-09-06

申请人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

发明人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

IPC分类号： G06F15/78 ,  G06F1/10 ,  H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

摘要翻译： 公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。 该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。 每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。 在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。 时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。 时钟门电路与每个逻辑单元中的输出多路复用器协同控制。 网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

公开(公告)号：US5703498A

公开(公告)日：1997-12-30

申请号：US709060

申请日：1996-09-06

申请人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

发明人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

IPC分类号： G06F15/78 ,  G06F1/10 ,  H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.

摘要翻译： 公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。 该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。 每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。 在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。 时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。 时钟门电路与每个逻辑单元中的输出多路复用器协同控制。 网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

公开(公告)号：US5652529A

公开(公告)日：1997-07-29

申请号：US459156

申请日：1995-06-02

申请人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

发明人： Scott Whitney Gould ,  Frederick Curtis Furtek ,  Frank Ray Keyser, III ,  Brian A. Worth ,  Terrance John Zittritsch

IPC分类号： G06F15/78 ,  G06F1/10 ,  H01L21/82 ,  H03K19/0175 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/1737 ,  H03K19/17704

摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering, and output driver sizing as a function of signal propagation distance.

摘要翻译： 公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。 该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。 每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。 在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。 时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。 时钟门电路与每个逻辑单元中的输出多路复用器协同控制。 网络被设计为具有最小化信号偏移的特征，包括信号源缓冲，多路复用器信号缓冲和作为信号传播距离的函数的输出驱动器尺寸。

公开(公告)号：US5646546A

公开(公告)日：1997-07-08

申请号：US460481

申请日：1995-06-02

申请人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

发明人： Allan Robert Bertolet ,  Kim P. N. Clinton ,  Christine Marie Fuller ,  Scott Whitney Gould ,  Steven Paul Hartman ,  Joseph Andrew Iadanza ,  Frank Ray Keyser ,  Eric Ernest Millham ,  Timothy Shawn Reny ,  Brian A. Worth ,  Gulson Yasar ,  Terrance John Zittritsch

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03F19/177

CPC分类号： H03K19/1737

摘要： A programmable logic cell has four logic gates, two of which are configurable. The two configurable logic gates are positioned near the logic cell inputs. Each configurable logic gate has two inputs, each input being connected to one of the four logic cell inputs. The remaining two logic gates receive the outputs of the configurable logic gates. Four independent logic cell input nodes are provided, each having associated therewith a programmable input multiplexer. Each input multiplexer can have inputs connected to at least two types of interconnect conductors. The cell also has two output paths, each having associated therewith an independently-controlled output multiplexer. The output of each output multiplexer is connected to an input of the other output multiplexer. Additional features include a multiplexer having inputs connected to two cell input nodes, a select input connected to a third logic cell input node, and an output connected to a cell output node; a system low-skew data (e.g., clock) input available to at least one of the input multiplexers; a flip-flop connected within the logic cell; and internal cell feedback. The preferred method of programming utilizes user-programmed SRAM memory cells.

摘要翻译： 可编程逻辑单元具有四个逻辑门，其中两个可配置。 两个可配置逻辑门位于逻辑单元输入附近。 每个可配置逻辑门具有两个输入，每个输入连接到四个逻辑单元输入之一。 剩余的两个逻辑门接收可配置逻辑门的输出。 提供四个独立的逻辑单元输入节点，每个具有与可编程输入多路复用器相关联的逻辑单元输入节点。 每个输入多路复用器可以具有连接到至少两种类型的互连导体的输入。 该单元还具有两个输出路径，每个输出路径与其相关联，具有独立控制的输出多路复用器。 每个输出多路复用器的输出连接到另一个输出多路复用器的输入端。 附加特征包括具有连接到两个单元输入节点的输入的多路复用器，连接到第三逻辑单元输入节点的选择输入和连接到单元输出节点的输出; 用于至少一个输入多路复用器的系统低偏移数据（例如，时钟）输入; 连接在逻辑单元内的触发器; 和内部单元反馈。 编程的首选方法利用用户编程的SRAM存储单元。