公开(公告)号：US4876501A

公开(公告)日：1989-10-24

申请号：US285362

申请日：1988-12-14

Applicant: Joseph L. Ardini ,  Brian Lefsky ,  Barbara J. Farr

Inventor： Joseph L. Ardini ,  Brian Lefsky ,  Barbara J. Farr

IPC: G01R31/30

CPC classification number: G01R31/3016

Abstract: Methods and apparatus for accurately measuring propagation delay through very high speed VLSI devices with a test instrument having errors comparable to the delays being measured. The VLSI device has a plurality of parallel operational signal paths, each with a very short propagation delay. The VLSI device is fabricated with control circuitry for selectively connecting the parallel operational signal paths in series in a test mode so as to define a test signal path comprising multiple operational signal paths. The test signal path has a relatively long propagation delay which can be measured with acceptable accuracy by the test instrument. The test signal path is defined so that it bypasses clocked circuit elements on the VLSI device. Since the operational signal paths are on the same integrated circuit and have very well correlated operating characteristics, the propagation delay through the test signal path is a good representation of the integrated circuit dynamic operation. When the integrated circuit is not in the test mode, the series connections are disabled and the parallel circuits operate in their normally intended manner. A minimum of circuitry is added to the VLSI device in order to implement the test mode.

Abstract translation: 用于通过具有与所测量的延迟相当的误差的测试仪器通过非常高速的VLSI器件精确地测量传播延迟的方法和装置。 VLSI设备具有多个并行操作信号路径，每个具有非常短的传播延迟。 用控制电路制造VLSI器件，用于以测试模式选择性地连接并联操作信号路径，以便定义包括多个操作信号路径的测试信号路径。 测试信号路径具有相对较长的传播延迟，可以通过测试仪器以可接受的精度进行测量。 定义测试信号路径，使其绕过VLSI设备上的时钟电路元件。 由于操作信号路径位于相同的集成电路上并且具有非常好的相关操作特性，所以通过测试信号路径的传播延迟是集成电路动态操作的良好表示。 当集成电路不在测试模式时，串联连接被禁用，并联电路以其正常的方式工作。 为了实现测试模式，向VLSI设备添加了最少的电路。

公开(公告)号：US5019971A

公开(公告)日：1991-05-28

申请号：US396785

申请日：1989-08-21

Applicant: Brian Lefsky ,  Mary E. Natusch

Inventor： Brian Lefsky ,  Mary E. Natusch

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F11/20 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/126 ,  G06F11/08 ,  G06F12/0864 ,  G06F11/10 ,  G06F2212/1032

Abstract: A high availability set associative cache memory for use as a buffer between a main memory and a central processing unit includes multiple sets of cache cells contained in two or more cache memory elements. Each of the cache cells includes a data field, a tag field and a status field. The status field includes a force bit which indicates a defective cache cell when it is set. Output from a cache cell is suppressed when its force bit is set. The defective cache cell is effectively mapped out so that data is not stored in it. As long as one cell in a set remains operational, the system can continue operation. The status field also includes an update bit which indicates the update status of the respective cache cell. Replacement selection logic examines the bit pattern in all the cache cells in a set and selects a cache cell to be replaced using a first-in first-out algorithm. The state of the update bit is changed each time the data in the respective cache cell is replaced unless the cache cell was modified on a previous store cycle.

Abstract translation: 用作主存储器和中央处理单元之间的缓冲器的高可用性组关联高速缓冲存储器包括包含在两个或多个高速缓存存储器元件中的多组高速缓存单元。 每个缓存单元包括数据字段，标签字段和状态字段。 状态字段包括强制位，其在设置时指示有缺陷的高速缓存单元。 当其强制位置1时，来自高速缓存单元的输出被抑制。 有效地映射有缺陷的高速缓存单元，使得数据不被存储在其中。 只要集合中的一个单元格保持运行，系统可以继续运行。 状态字段还包括指示相应高速缓存单元的更新状态的更新位。 替换选择逻辑检查集合中所有高速缓存单元中的位模式，并使用先进先出算法选择要替换的高速缓存单元。 每次更新相应高速缓存单元中的数据时，更新位的状态将被更改，除非高速缓存单元在先前的存储周期中被修改。

公开(公告)号：US4750154A

公开(公告)日：1988-06-07

申请号：US629349

申请日：1984-07-10

Applicant: Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

Inventor： Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

IPC: G06F5/06 ,  G06F9/312 ,  G06F9/38 ,  G06F13/16 ,  G06F13/42 ,  G11C5/00

CPC classification number: G06F9/30043 ,  G06F13/1631 ,  G06F13/4234 ,  G06F5/065 ,  G06F9/3824 ,  G06F9/3826

Abstract: A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

Abstract translation: 公开了一种存储器对准系统和方法，其具有设计成一次容纳多于一个写指令的存储器总线，并且当写入目的地是存储器中可对准位置时，来自不同写指令的数据被合并在一起。 在一个实施例中，写缓冲器和比较器被配置为比较可对准目的地地址的连续指令。 在另一个实施例中，使用内容关联缓冲器来将写指令的地址与所有其它存储的写指令的地址进行比较。 还公开了一种用于控制缓冲器卸载的可变调度器，用于将从存储器读取的数据与等待传输到存储器的数据合并以获得最新版本的装置。

公开(公告)号：US4949249A

公开(公告)日：1990-08-14

申请号：US390471

申请日：1989-08-03

Applicant: Brian Lefsky ,  Joseph L. Ardini, Jr. ,  Michael Schwartz

Inventor： Brian Lefsky ,  Joseph L. Ardini, Jr. ,  Michael Schwartz

IPC: G06F1/10 ,  G06F9/38

CPC classification number: G06F1/10 ,  G06F9/3869

Abstract: A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

Abstract translation: 一种用于提供偏移补偿的技术，特别是与流水线处理器相关联。 偏移发生在第一和第二时钟信号之间。 本发明的偏斜补偿技术即使时钟信号可能具有比阶段间延迟更大的偏差，也可以提供阶段之间的信息的适当传递。 在级之间提供保持或锁存装置，以便保持前一级数据用于计时到后级级寄存器。

公开(公告)号：US4888687A

公开(公告)日：1989-12-19

申请号：US46456

申请日：1987-05-04

Applicant: Robert Allison ,  Brian Lefsky

Inventor： Robert Allison ,  Brian Lefsky

IPC: G06F12/06

CPC classification number: G06F12/0684 ,  G06F12/0661

Abstract: A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.