公开(公告)号：US08530317B1

公开(公告)日：2013-09-10

申请号：US13587123

申请日：2012-08-16

申请人： Po-Chi Wu ,  Buh-Kuan Fang

发明人： Po-Chi Wu ,  Buh-Kuan Fang

IPC分类号： H01L21/336

CPC分类号： H01L29/4232 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/7833

摘要： A replacement gate process for fabricating a semiconductor device with metal gates includes forming a dummy gate stack, patterning dummy gates, doping source and drain regions for the gates, and forming an inter-level dielectric layer that overlays the source and drain regions. The sacrificial layer of the dummy gates is removed to form trenches using a three stage process. The first stage begins the trenches, whereby trenches entrance corners are exposed. The second stage is an etch that rounds the corners. The third stage is a main etch for the sacrificial layer, which is typically polysilicon. The corner rounding of the second stage improves the performance of the third stage and results in a better metal back fill including a reduction in pit defects. The process improves overall device yield in comparison to an otherwise equivalent process that omits the corner rounding step.

摘要翻译： 用于制造具有金属栅极的半导体器件的替代栅极工艺包括形成伪栅极堆叠，图案化伪栅极，用于栅极的掺杂源极和漏极区域，以及形成覆盖源极和漏极区域的层间电介质层。 去除伪栅极的牺牲层以使用三阶段工艺形成沟槽。 第一阶段开始沟渠，沟渠入口角落暴露。 第二阶段是一个刻蚀角落的蚀刻。 第三阶段是用于牺牲层的主要蚀刻，其通常是多晶硅。 第二阶段的圆角改善了第三阶段的性能，并且导致更好的金属回填，包括减少凹坑缺陷。 与省略角舍入步骤的其他等效过程相比，该过程提高了整体设备产量。

公开(公告)号：US20130146993A1

公开(公告)日：2013-06-13

申请号：US13314462

申请日：2011-12-08

申请人： Che-Cheng CHANG ,  Po-chi WU ,  Buh-Kuan FANG ,  Jr-Jung LIN ,  Ryan Chia-Jen CHEN

发明人： Che-Cheng CHANG ,  Po-chi WU ,  Buh-Kuan FANG ,  Jr-Jung LIN ,  Ryan Chia-Jen CHEN

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843

摘要： The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

摘要翻译： 本申请公开了一种形成半导体结构的方法。 在至少一个实施例中，该方法包括在衬底上形成多晶硅层。 在多晶硅层上形成掩模层。 图案化掩模层以形成图案化掩模层。 通过使用图案化掩模层作为掩模蚀刻多晶硅层来形成多晶硅结构。 多晶硅结构具有上表面和下表面，并且多晶硅层的蚀刻被布置成使得多晶硅结构的上表面的宽度大于多晶硅结构的下表面的宽度。

公开(公告)号：US20130084685A1

公开(公告)日：2013-04-04

申请号：US13250483

申请日：2011-09-30

申请人： Buh-Kuan Fang

发明人： Buh-Kuan Fang

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L21/266

摘要： Methods for ion implantation. A method comprises forming a layer of non-crosslinking mask material over a semiconductor region; forming a patterned photoresist layer over the non-crosslinking mask layer; removing the photoresist layer and the non-crosslinking mask layer from the exposed regions, while the masked regions remain covered; and implanting dopant ions into the exposed regions, the dopant ions being blocked from the masked regions. The non-crosslinking mask layer and any remaining photoresist material may be removed. In additional embodiments, the non-crosslinking material comprises carbon. In another embodiment, the non-crosslinking material comprises an oxide. Ion implantations for source and drain, lightly doped drain, and well regions are performed.

摘要翻译： 离子注入方法 一种方法包括在半导体区域上形成非交联掩模材料层; 在所述非交联掩模层上形成图案化的光致抗蚀剂层; 从曝光区域去除光致抗蚀剂层和非交联掩模层，同时掩蔽区域保持覆盖; 并且将掺杂剂离子注入到暴露区域中，所述掺杂剂离子被阻挡在掩蔽区域上。 可以除去非交联掩模层和任何剩余的光致抗蚀剂材料。 在另外的实施方案中，非交联材料包含碳。 在另一个实施方案中，非交联材料包含氧化物。 进行离子注入用于源极和漏极，轻掺杂漏极和阱区。

公开(公告)号：US08574989B2

公开(公告)日：2013-11-05

申请号：US13314462

申请日：2011-12-08

申请人： Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

发明人： Che-Cheng Chang ,  Po-Chi Wu ,  Buh-Kuan Fang ,  Jr-Jung Lin ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7843

摘要： The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

摘要翻译： 本申请公开了一种形成半导体结构的方法。 在至少一个实施例中，该方法包括在衬底上形成多晶硅层。 在多晶硅层上形成掩模层。 图案化掩模层以形成图案化掩模层。 通过使用图案化掩模层作为掩模蚀刻多晶硅层来形成多晶硅结构。 多晶硅结构具有上表面和下表面，并且多晶硅层的蚀刻被布置成使得多晶硅结构的上表面的宽度大于多晶硅结构的下表面的宽度。

公开(公告)号：US20050029221A1

公开(公告)日：2005-02-10

申请号：US10637360

申请日：2003-08-09

申请人： Fa-Yuan Chang ,  Buh-Kuan Fang ,  Shih-Feng Chen ,  Cheng-Cheng Chang

发明人： Fa-Yuan Chang ,  Buh-Kuan Fang ,  Shih-Feng Chen ,  Cheng-Cheng Chang

IPC分类号： C23F1/00

CPC分类号： B81C1/00619

摘要： A process for etching deep trenches in a substrate for purposes such as the fabrication of microelectromechanical systems (MEMS), for example, on the substrate. The two-step process includes first etching a tapered trench having a tapered profile and enhanced sidewall passivation in a substrate along a protective mask which defines the desired trench profile on the substrate surface. Next, the tapered trench is trimmed by high-density plasma in an isotropic etching step to provide a straight-profile deep trench with minimum sidewall passivation.

摘要翻译： 用于蚀刻基板中的深沟槽的方法，例如在基板上制造微机电系统（MEMS）。 两步工艺包括首先沿着保护掩模在衬底中蚀刻具有锥形轮廓和增强的侧壁钝化的锥形沟槽，所述保护掩模在衬底表面上限定所需的沟槽轮廓。 接下来，在各向同性蚀刻步骤中通过高密度等离子体修剪锥形沟槽，以提供具有最小侧壁钝化的直轮廓深沟槽。

公开(公告)号：US06835233B2

公开(公告)日：2004-12-28

申请号：US10371457

申请日：2003-02-20

申请人： Buh-Kuan Fang

发明人： Buh-Kuan Fang

IPC分类号： B01D4600

CPC分类号： H01L21/67126 ,  H01L21/67017

摘要： A method and device for gradually equalizing air or gas pressures between substrate processing chambers prior to transfer of a substrate between the chambers. The device comprises a gas flow restrictor provided in the chamber wall that separates the chambers. A door typically reversibly seals the gas flow restrictor. During substrate processing in one of the chambers, the gas flow restrictor is sealed to maintain a partial vacuum pressure in the chamber. Prior to opening the wafer transfer gate between the chambers, the gas flow restrictor door is opened to facilitate the gradual flow of air or gas from the higher-pressure chamber, through the gas flow restrictor to the lower-pressure chamber and substantially equalize the pressures in the respective chambers.