公开(公告)号：US20150187790A1

公开(公告)日：2015-07-02

申请号：US14643527

申请日：2015-03-10

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙比第二垂直间隙宽 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US08987805B2

公开(公告)日：2015-03-24

申请号：US13971347

申请日：2013-08-20

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US20120295409A1

公开(公告)日：2012-11-22

申请号：US13475023

申请日：2012-05-18

申请人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

发明人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L27/11582 ,  H01L21/31 ,  H01L29/7926

摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

摘要翻译： 制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于 第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除 所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

公开(公告)号：US09431414B2

公开(公告)日：2016-08-30

申请号：US14517025

申请日：2014-10-17

申请人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

发明人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11565 ,  H01L27/1158 ,  H01L29/66833 ,  H01L29/7926

摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

摘要翻译： 非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。 电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。 此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

公开(公告)号：US09324730B2

公开(公告)日：2016-04-26

申请号：US14601496

申请日：2015-01-21

申请人： Phil-Ouk Nam ,  Dong-Chul Yoo ,  Bi-O Kim ,  Jae-Young Ahn ,  Byong-Hyun Jang ,  Ki-Hyun Hwang

发明人： Phil-Ouk Nam ,  Dong-Chul Yoo ,  Bi-O Kim ,  Jae-Young Ahn ,  Byong-Hyun Jang ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/02

CPC分类号： H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

摘要翻译： 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US20140054676A1

公开(公告)日：2014-02-27

申请号：US13971347

申请日：2013-08-20

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US20150206900A1

公开(公告)日：2015-07-23

申请号：US14601496

申请日：2015-01-21

申请人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

发明人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

摘要翻译： 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US09082659B1

公开(公告)日：2015-07-14

申请号：US14643527

申请日：2015-03-10

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US08697498B2

公开(公告)日：2014-04-15

申请号：US13284435

申请日：2011-10-28

申请人： Byong-hyun Jang ,  Dongchul Yoo ,  Chanjin Park ,  Hanmei Choi

发明人： Byong-hyun Jang ,  Dongchul Yoo ,  Chanjin Park ,  Hanmei Choi

IPC分类号： H01L21/82 ,  H01L21/00

CPC分类号： H01L21/762 ,  H01L21/76224 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.

摘要翻译： 可以通过在板堆叠结构中形成至少一个沟槽来形成制造三维（3D）半导体存储器件的方法，以在形成多个垂直有源图案之间将板堆叠结构分成多个子板堆叠结构 在板堆叠结构中和从板堆叠结构的阶梯结构的成形垫。

公开(公告)号：US09397114B2

公开(公告)日：2016-07-19

申请号：US13475023

申请日：2012-05-18

申请人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

发明人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

IPC分类号： H01L27/00 ,  H01L21/00 ,  H01L27/115 ,  H01L21/31 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L21/31 ,  H01L29/7926

摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

摘要翻译： 制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于 第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除 所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。