公开(公告)号：US20190013328A1

公开(公告)日：2019-01-10

申请号：US15871059

申请日：2018-01-14

Applicant: Sung Gil KIM ,  Seul Ye KIM ,  Hong Suk KIM ,  Jin Tae NOH ,  Ji Hoon CHOI ,  Jae Young AHN

Inventor： Sung Gil KIM ,  Seul Ye KIM ,  Hong Suk KIM ,  Jin Tae NOH ,  Ji Hoon CHOI ,  Jae Young AHN

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/108 ,  H01L29/06 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L27/11582 ,  H01L23/53295 ,  H01L24/29 ,  H01L25/065 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/11565 ,  H01L29/0649

Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

公开(公告)号：US20180108672A1

公开(公告)日：2018-04-19

申请号：US15484339

申请日：2017-04-11

Applicant: Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20180040628A1

公开(公告)日：2018-02-08

申请号：US15462933

申请日：2017-03-20

Applicant: Phil-ouk Nam ,  Sung-gil KIM ,  Ji-hoon CHOI ,  SeuI-ye KIM ,  Jae-young AHN ,  Hong-suk KIM

Inventor： Phil-ouk Nam ,  Sung-gil KIM ,  Ji-hoon CHOI ,  SeuI-ye KIM ,  Jae-young AHN ,  Hong-suk KIM

IPC: H01L27/11582 ,  H01L29/78 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7827

Abstract: A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.

公开(公告)号：US09258808B2

公开(公告)日：2016-02-09

申请号：US13529310

申请日：2012-06-21

Applicant: Tae Gyun Noh ,  Young Jo Ko ,  Bang Won Seo ,  Jae Young Ahn

Inventor： Tae Gyun Noh ,  Young Jo Ko ,  Bang Won Seo ,  Jae Young Ahn

IPC: H04W72/04 ,  H04W4/20 ,  H04L5/00

Abstract: A method of transmitting and receiving a control channel in a wireless communication system is provided. A base station allocates a data channel to a radio resource, adds start position information of the data channel into a payload of a control channel, and performs signaling for indication information on the start position information added into the payload of the control channel to a terminal. Accordingly, the legacy system and the enhanced system can efficiently transmit a control channel.

公开(公告)号：US09240357B2

公开(公告)日：2016-01-19

申请号：US14100651

申请日：2013-12-09

Applicant: Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

Inventor： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC: H01L21/66 ,  H01L21/265 ,  H01L21/311 ,  H01L27/115

CPC classification number: H01L22/12 ,  H01L21/31116 ,  H01L22/20 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

Abstract translation: 根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。 扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

公开(公告)号：US20150206900A1

公开(公告)日：2015-07-23

申请号：US14601496

申请日：2015-01-21

Applicant: Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

Inventor： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

Abstract translation: 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US09082659B1

公开(公告)日：2015-07-14

申请号：US14643527

申请日：2015-03-10

Applicant: Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

Inventor： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

Abstract translation: 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US20150137210A1

公开(公告)日：2015-05-21

申请号：US14546172

申请日：2014-11-18

Applicant: Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

Inventor： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

Abstract translation: 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

公开(公告)号：US20140239375A1

公开(公告)日：2014-08-28

申请号：US14182325

申请日：2014-02-18

Applicant: Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

Inventor： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

Abstract: A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

Abstract translation: 垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。 通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上依次形成在每个沟道的侧壁上。 所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。 虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

公开(公告)号：US08660601B2

公开(公告)日：2014-02-25

申请号：US13059903

申请日：2009-08-14

Applicant: Bangwon Seo ,  Young Jo Ko ,  Jae Young Ahn

Inventor： Bangwon Seo ,  Young Jo Ko ,  Jae Young Ahn

IPC: H04B7/00 ,  H04B1/00

CPC classification number: H04B7/024 ,  H04B7/0413 ,  H04B7/0426 ,  H04B7/0617 ,  H04B7/0639 ,  H04B7/0671

Abstract: Provided is a communication system for a multi-cell cooperative communication. A serving base station and at least one neighboring base station may communicate with at least one terminal through mutual cooperation. Each of the serving base station and the at least one neighboring base station may shift a phase of at least one element among elements included in a precoding matrix, using a phase shift matrix, and precode at least one data symbol. A terminal may feed back preferred phase shift matrix information to the serving base station, so that the serving base station and the at least one neighboring base station may adaptively determine a phase shift matrix. The terminal may calculate the phase shift matrix with small calculation amounts. The serving base station, the at least one neighboring base station, and the terminal may pre-store a plurality of candidate matrices with respect to the phase shift matrix.

Abstract translation: 提供了一种用于多小区协作通信的通信系统。 服务基站和至少一个相邻基站可以通过相互协作与至少一个终端进行通信。 服务基站和至少一个相邻基站中的每个可以使用相移矩阵来移位包括在预编码矩阵中的元素中的至少一个元素的相位，并且对至少一个数据符号进行预编码。 终端可以将优选的相移矩阵信息反馈到服务基站，使得服务基站和至少一个相邻基站可以自适应地确定相移矩阵。 终端可以以较小的计算量计算相移矩阵。 服务基站，至少一个相邻基站和终端可以相对于相移矩阵预存储多个候选矩阵。