公开(公告)号：US08268092B2

公开(公告)日：2012-09-18

申请号：US12841347

申请日：2010-07-22

申请人： Jae Suk Yang ,  Hyeon Chul Lim ,  Byoung Ki Lee ,  Yong Sup Lee ,  Yong Hyun Kim ,  Yong Sul Song ,  Sang Kyun Kwon ,  Beom Jin Kim

发明人： Jae Suk Yang ,  Hyeon Chul Lim ,  Byoung Ki Lee ,  Yong Sup Lee ,  Yong Hyun Kim ,  Yong Sul Song ,  Sang Kyun Kwon ,  Beom Jin Kim

IPC分类号： H01F1/147 ,  H01F1/16

CPC分类号： G06K19/07771 ,  H01Q1/22 ,  H01Q17/00

摘要： Provided are a magnetic sheet for use in a radio frequency identification (RFID) antenna, an RFID antenna including the magnetic sheet, and a method of manufacturing the magnetic sheet, in which the magnetic sheet includes an amorphous alloy selected from the group consisting of Fe—Si—B, Fe—Si—B—Cu—Nb, Fe—Zr—B and Co—Fe—Si—B. The magnetic sheet is made by laminating amorphous alloy ribbons made of an amorphous alloy between magnetic sheet layers formed of alloy powder including at least one amorphous alloy and then compression-molding the amorphous alloy ribbons, to thereby control microcrack of the amorphous alloy ribbons and enhance characteristic of an end-product. The magnetic sheet is also thin, and has an excellent magnetic permeability, and a simple manufacturing process.

摘要翻译： 提供了一种用于射频识别（RFID）天线的磁性片，包括该磁性片的RFID天线，以及制造该磁性片的方法，其中该磁性片包括选自Fe -Si-B，Fe-Si-B-Cu-Nb，Fe-Zr-B和Co-Fe-Si-B。 该磁性片是通过在由包括至少一种非晶态合金的合金粉末形成的磁性层之间层叠由非晶合金制成的非晶合金带，然后压制非晶态合金带的方法制成的，从而控制非晶合金带的微裂纹并增强 最终产品的特点。 磁性薄片也薄，并且具有优异的导磁率和简单的制造工艺。

公开(公告)号：US20100181608A1

公开(公告)日：2010-07-22

申请号：US12607183

申请日：2009-10-28

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： According to the present disclosure, a flash memory device includes a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.

摘要翻译： 根据本公开，闪存器件包括半导体衬底，其包括选择晶体管区域和限定在选择晶体管区域，形成在选择晶体管区域中的第一隔离层和形成在存储单元中的第二隔离层之间的存储单元区域 地区。 第二隔离层的高度比第一隔离层低。

公开(公告)号：US20080003749A1

公开(公告)日：2008-01-03

申请号：US11768722

申请日：2007-06-26

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42376

摘要： A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：通过在半导体衬底上形成隧道氧化物层和用于浮置栅极的导电层来形成沟槽，然后蚀刻导电层，隧道氧化物层和半导体的一部分 衬底以形成沟槽，用绝缘层填充沟槽以形成在浮置栅极上方突出的隔离层，在浮置栅极上方突出的隔离层的侧壁上形成间隔物，使用间隔物作为掩模蚀刻导电层，由此形成 U形导电层，去除间隔物，蚀刻隔离层的顶表面，从而控制隔离层的有效场高（EFH），并在所得到的栅极上形成介电层和导电层 表面。

公开(公告)号：US08216899B2

公开(公告)日：2012-07-10

申请号：US12607183

申请日：2009-10-28

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： According to the present disclosure, a flash memory device includes a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.

摘要翻译： 根据本公开，闪存器件包括半导体衬底，其包括选择晶体管区域和限定在选择晶体管区域，形成在选择晶体管区域中的第一隔离层和形成在存储单元中的第二隔离层之间的存储单元区域 地区。 第二隔离层的高度比第一隔离层低。

公开(公告)号：USRE42409E1

公开(公告)日：2011-05-31

申请号：US12800858

申请日：2010-05-24

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42376

摘要： A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：通过在半导体衬底上形成隧道氧化物层和用于浮置栅极的导电层来形成沟槽，然后蚀刻导电层，隧道氧化物层和半导体的一部分 衬底以形成沟槽，用绝缘层填充沟槽以形成在浮置栅极上方突出的隔离层，在浮置栅极上方突出的隔离层的侧壁上形成间隔物，使用间隔物作为掩模蚀刻导电层，由此形成 U形导电层，去除间隔物，蚀刻隔离层的顶表面，从而控制隔离层的有效场高（EFH），并在所得到的栅极上形成介电层和导电层 表面。

公开(公告)号：US07563674B2

公开(公告)日：2009-07-21

申请号：US11605130

申请日：2006-11-28

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a NAND flash memory device, wherein isolation layers are formed in a semiconductor substrate, and an upper side of each of the isolation layers is made to have a negative profile. A polysilicon layer is formed on the entire surface. At this time, a seam is formed within the polysilicon layer due to the negative profile. A post annealing process is performed in order to make the seam to a void. Accordingly, an electrical interference phenomenon between cells can be reduced and a threshold voltage (Vt) shift value can be lowered.

摘要翻译： 一种制造NAND闪速存储器件的方法，其中在半导体衬底中形成隔离层，并且使每个隔离层的上侧具有负轮廓。 在整个表面上形成多晶硅层。 此时，由于阴性轮廓，在多晶硅层内形成接缝。 进行后退火处理以使接缝成为空隙。 因此，可以减小电池之间的电气干扰现象，并且可以降低阈值电压（Vt）偏移值。

公开(公告)号：US5648957A

公开(公告)日：1997-07-15

申请号：US388973

申请日：1995-02-15

申请人： Byoung ki Lee ,  Jung-kyu Lee

发明人： Byoung ki Lee ,  Jung-kyu Lee

IPC分类号： H04Q3/00 ,  H04L12/931 ,  H04L12/933 ,  H04L12/937 ,  H04Q3/52 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/1561 ,  H04L49/255 ,  H04L2012/5681

摘要： A distributor with controlled switching elements (CSE) which simplifies hardware construction by distributing the function of a running adder into a reverse banyan network. The distributor comprises a CSE-based network using switching stages, each switching stage having control switching elements. A control signal input stage switches two packet input signal switching channels, each stage receiving each control signal from an output stage having switching elements. An active packet counter counts and generates an output signal which represents the number of active packets inputted to the CSE network. A tail-of-queue register is used for storing output vectors.

摘要翻译： 具有受控开关元件（CSE）的分配器，其通过将运行中的加法器的功能分配到反向榕树网络来简化硬件构造。 分配器包括使用开关级的基于CSE的网络，每个开关级具有控制开关元件。 控制信号输入级切换两个分组输入信号切换通道，每个级从具有开关元件的输出级接收每个控制信号。 活动分组计数器计数并产生表示输入到CSE网络的活动分组的数量的输出信号。 队列尾寄存器用于存储输出向量。

公开(公告)号：US20120211817A1

公开(公告)日：2012-08-23

申请号：US13462340

申请日：2012-05-02

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L27/11

CPC分类号： H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A flash memory device including a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers.

摘要翻译： 一种闪速存储器件，包括包括选择晶体管区域和限定在选择晶体管区域之间的存储单元区域，形成在选择晶体管区域中的第一隔离层和形成在存储单元区域中的第二隔离层的半导体衬底。 第二隔离层的高度比第一隔离层低。

公开(公告)号：US07696043B2

公开(公告)日：2010-04-13

申请号：US11768722

申请日：2007-06-26

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42376

摘要： A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.

摘要翻译： 一种制造闪速存储器件的方法包括以下步骤：通过在半导体衬底上形成隧道氧化物层和用于浮置栅极的导电层来形成沟槽，然后蚀刻导电层，隧道氧化物层和半导体的一部分 衬底以形成沟槽，用绝缘层填充沟槽以形成在浮置栅极上方突出的隔离层，在浮置栅极上方突出的隔离层的侧壁上形成间隔物，使用间隔物作为掩模蚀刻导电层，由此形成 U形导电层，去除间隔物，蚀刻隔离层的顶表面，从而控制隔离层的有效场高（EFH），并在所得到的栅极上形成介电层和导电层 表面。

公开(公告)号：US07544567B2

公开(公告)日：2009-06-09

申请号：US11752875

申请日：2007-05-23

申请人： Byoung Ki Lee

发明人： Byoung Ki Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/11573 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

摘要： In a method of manufacturing an SONOS type flash memory device, a first oxide layer and a buffer poly layer are formed over a surface of a semiconductor except for a memory cell region of a cell region. A second oxide layer, a nitride layer and a third oxide layer are formed. The poly buffer layer is exposed by etching specific regions in a peri region and in a DSL/SSL region of the cell region. A conductive layer is formed to electrically connect to the poly buffer layer. The third oxide layer, the nitride layer and the second nitride layer are selectively etched to form a gate of the memory cell region of the cell region. The buffer poly layer is selectively etched to form a gate in the DSL/SSL region of the cell region and a gate in the peri region.

摘要翻译： 在制造SONOS型闪速存储器件的方法中，除了单元区域的存储单元区域之外，在半导体的表面上形成第一氧化物层和缓冲多晶硅层。 形成第二氧化物层，氮化物层和第三氧化物层。 多缓冲层通过蚀刻细胞区域的周边区域和DSL / SSL区域中的特定区域而暴露。 形成导电层以电连接到多缓冲层。 选择性地蚀刻第三氧化物层，氮化物层和第二氮化物层以形成电池区域的存储单元区域的栅极。 选择性地蚀刻缓冲多晶硅层以在单元区域的DSL / SSL区域中形成栅极，并在周边区域形成栅极。