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公开(公告)号：US10074668B2
公开(公告)日：2018-09-11
申请号：US15622648
申请日：2017-06-14
IPC分类号： H01L27/118 , H01L29/66 , H01L29/78 , H01L29/08
CPC分类号： H01L27/11807 , H01L21/31116 , H01L21/31155 , H01L21/32135 , H01L21/32155 , H01L21/823431 , H01L21/823468 , H01L29/0847 , H01L29/66545 , H01L29/66803 , H01L29/7851 , H01L2027/11853 , H01L2027/11864
摘要： A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.
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2.发明申请公开(公告)号：US20180208456A1
公开(公告)日：2018-07-26
申请号：US15745897
申请日：2016-07-21
申请人： DNP123 Company
发明人： Aaron T. Santos , Derek M. Lyons
CPC分类号： B81B7/0003 , A61K9/14 , B22F1/0044 , B22F1/0062 , B22F9/24 , B22F2301/255 , B81C1/00007 , B81C2201/0149 , B82B3/0047 , B82Y5/00 , B82Y40/00 , C07H21/04 , C25B9/16 , H01L27/11807 , H01L2027/11853
摘要： The present invention generally relates to nanofabrication and, in some embodiments, to methods of synthesizing selectively binding patched nanoparticles and the devices that can be made from them. In some embodiments, the invention relates to methods of assembling arbitrarily shaped structures from patched nanocubes and the devices and uses that follow. For example, nanocube building blocks may be patched by stamping their faces with a selectively binding chemical species (e.g. DNA, antibody-antigen pairs, etc.), or by using self-assembly to attach to the nanocubes multiple selectively binding patch species whose immiscibility can be preprogrammed. Arbitrarily shaped structures can then be designed and assembled by deciding which faces will be bonded to each other in some target structure and combining nanocubes that have selectively binding patches on those faces. Other aspects of the invention are also directed to methods of making such nanocubes or other nanoparticles, methods of forming such nanocubes.
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3.发明申请公开(公告)号：US20170278865A1
公开(公告)日：2017-09-28
申请号：US15622648
申请日：2017-06-14
IPC分类号： H01L27/118 , H01L29/78 , H01L29/08 , H01L29/66
CPC分类号： H01L27/11807 , H01L21/31116 , H01L21/31155 , H01L21/32135 , H01L21/32155 , H01L21/823431 , H01L21/823468 , H01L29/0847 , H01L29/66545 , H01L29/66803 , H01L29/7851 , H01L2027/11853 , H01L2027/11864
摘要： A semiconductor device includes a first FinFET device and a second FinFET device. The first FinFET device includes a first gate, a first source, and a first drain. The first FinFET device has a first source/drain proximity. The second FinFET device includes a second gate, a second source, and a second drain. The second FinFET device has a second source/drain proximity that is smaller than the first source/drain proximity. In some embodiments, \the first FinFET device is an Input/Output (I/O) device, and the second FinFET device is a non-I/O device such as a core device. In some embodiments, the greater source/drain proximity of the first FinFET device is due to an extra spacer of the first FinFET device that does not exist for the second FinFET device.
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4.发明授权Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods 有权包括数字逻辑电路的半导体芯片包括至少六个晶体管，其中一些晶体管形成交叉耦合晶体管配置和相关方法公开(公告)号：US09213792B2
公开(公告)日：2015-12-15
申请号：US14642633
申请日：2015-03-09
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/11 , G06F17/50 , H01L27/02 , H01L27/092 , H01L27/088 , H01L23/538 , H01L27/118 , H01L23/498
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and one or more conductive interconnect structures.
摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。 第一和第二晶体管类型的第二晶体管的栅极电极通过包括各个栅极触点和一个或多个导电互连结构的电连接彼此电连接。
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5.发明授权Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer 有权交叉耦合晶体管电路具有通过单互连层的相同栅极电极轨道和栅极节点连接的相对侧上的公共节点的扩散区域公开(公告)号：US09081931B2
公开(公告)日：2015-07-14
申请号：US13831742
申请日：2013-03-15
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/088 , G06F17/50 , H01L27/02 , H01L27/092 , H01L23/538 , H01L27/118 , H01L23/498
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极通过由线性导电结构形成的电连接彼此电连接。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。
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6.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications 有权集成电路包括交叉耦合晶体管，其栅极电极形成在具有栅电极放置规格的栅极级特征布局通道内公开(公告)号：US08835989B2
公开(公告)日：2014-09-16
申请号：US12754566
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes.
摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 导电特征各自定义在与多个平行栅极电极轨道中的一个唯一相关联并且沿着多个平行栅极电极轨迹中的一个限定的任何一个门级通道内。 导电特征分别形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第二NMOS晶体管器件的栅电极部分地由第一互连电平内的第一导体电连接。 第二PMOS和第一NMOS晶体管器件的栅电极部分地由第一互连级内的第二导体电连接。 第一PMOS，第二PMOS，第一NMOS和第二NMOS晶体管器件限定具有共同取向的栅电极的交叉耦合晶体管配置。
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7.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts 有权集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，具有外部定位的栅极触点公开(公告)号：US08742463B2
公开(公告)日：2014-06-03
申请号：US12754215
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10 , H01L27/02 , H01L27/088 , H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. A gate electrode level region is formed in accordance with a virtual grate defined by virtual lines that extend in only a first parallel direction, such that an equal perpendicular spacing exists between adjacent ones of the virtual lines. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of virtual lines of the virtual grate. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected, and the gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected.
摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 根据由只在第一平行方向延伸的虚拟线限定的虚拟格栅形成栅极电平区域，使得相邻虚拟线之间存在相等的垂直间隔。 导电特征各自定义在与虚拟炉排的多条虚拟线路中的一条唯一相关联并定义的任何一个门级通道内。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第二NMOS晶体管器件的栅电极电连接，并且第二PMOS和第一NMOS晶体管器件的栅电极电连接。
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8.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships 有权集成电路包括交叉耦合晶体管，其具有形成在栅极级特征布局通道内的栅电极，其具有具有偏移和对准关系的四个内部定位的栅极触点公开(公告)号：US08581304B2
公开(公告)日：2013-11-12
申请号：US12753810
申请日：2010-04-02
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
摘要翻译： 半导体器件包括栅极电极区域内的导电特征，每个导电特征各自由相应的起始矩形布局特征制成，其中心线平行于第一方向排列。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS，第二PMOS，第一NMOS和第二NMOS晶体管器件的栅电极分别沿着不同的栅电极轨道延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。
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9.发明申请Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts 有权交叉耦合晶体管电路定义为具有至少两个非内部定位栅极触点的相同栅电极轨道的相对侧上的公共节点的扩散区域公开(公告)号：US20130200465A1
公开(公告)日：2013-08-08
申请号：US13831832
申请日：2013-03-15
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： G06F17/50 , H01L27/088
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes two conductive contacting structures at a location not over an inner non-diffusion region.
摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。 第一和第二晶体管类型的第二晶体管的栅极电极通过电连接彼此电连接，该电连接在不在内部非扩散区域的位置处包括两个导电接触结构。
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10.发明申请Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer 审中-公开交叉耦合晶体管电路具有相同栅极电极的相对侧上的公共节点的扩散区域，通过单互连层连接栅极节点公开(公告)号：US20130193524A1
公开(公告)日：2013-08-01
申请号：US13831742
申请日：2013-03-15
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极通过由线性导电结构形成的电连接彼此电连接。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。
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