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1.发明授权System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method 有权使用计算系统设计半导体封装的系统和方法，用于制造包括该系统的半导体封装的装置，以及通过该方法设计的半导体封装公开(公告)号：US09465900B2
公开(公告)日：2016-10-11
申请号：US14064102
申请日：2013-10-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/40 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/1432 , H01L2924/1436 , H01L2924/15311 , H01L2924/15331
摘要： A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.
摘要翻译： 一种使用计算系统设计半导体封装的系统，包括：虚拟堆叠模块，被配置为接收第一芯片的布局参数，第二芯片的布局参数和用于封装衬底的布局参数，并且响应于 第一芯片，第二芯片和封装基板的布局参数在封装基板上产生堆叠第一和第二芯片的多个虚拟布局; 建模模块，被配置为响应于所述虚拟布局来建模所述第一和第二芯片和所述封装衬底的操作参数; 以及特征分析模块，被配置为响应于建模的操作参数来分析虚拟布局的操作特性。
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2.发明申请SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTING SYSTEM, APPARATUS FOR FABRICATING SEMICONDUCTOR PACKAGE INCLUDING THE SYSTEM, AND SEMICONDUCTOR PACKAGE DESIGNED BY THE METHOD 有权使用计算系统设计半导体封装的系统和方法，用于制造包括系统的半导体封装的装置，以及由该方法设计的半导体封装公开(公告)号：US20140131867A1
公开(公告)日：2014-05-15
申请号：US14064102
申请日：2013-10-25
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/40 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/1432 , H01L2924/1436 , H01L2924/15311 , H01L2924/15331
摘要： A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.
摘要翻译： 一种使用计算系统设计半导体封装的系统，包括：虚拟堆叠模块，被配置为接收第一芯片的布局参数，第二芯片的布局参数和用于封装衬底的布局参数，并且响应于 第一芯片，第二芯片和封装基板的布局参数在封装基板上产生堆叠第一和第二芯片的多个虚拟布局; 建模模块，被配置为响应于所述虚拟布局来建模所述第一和第二芯片和所述封装衬底的操作参数; 以及特征分析模块，被配置为响应于建模的操作参数来分析虚拟布局的操作特性。
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公开(公告)号：US06539528B2
公开(公告)日：2003-03-25
申请号：US09826579
申请日：2001-04-05
申请人： Chan-seok Hwang , Yong-jin Lee , Dae-hee Lee , Jong-bae Lee
发明人： Chan-seok Hwang , Yong-jin Lee , Dae-hee Lee , Jong-bae Lee
IPC分类号： G06F945
CPC分类号： G06F17/5068
摘要： An integrated circuit (IC) is designed by generating a circuit diagram of the IC using one or more blocks. An information repository is provided that contains layout information that is associated with one or more template blocks. A symbol layout abstraction model is then generated by associating the layout information that is associated with one or more of the template blocks with at least one of the circuit diagram blocks of the IC.
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