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    Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages
    2.
    发明授权
    Methods, apparatus and computer program products for generating selective netlists that include interconnection influences at pre-layout and post-layout design stages 有权
    用于生成选择性网表的方法，设备和计算机程序产品，其中包括在布局前布局和布局后设计阶段的互连影响

    公开(公告)号：US07159202B2

    公开(公告)日：2007-01-02

    申请号：US10629154

    申请日：2003-07-29

    申请人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

    发明人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5068

    摘要： Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic.

    摘要翻译： 用于产生集成电路网表的操作包括生成其中具有多个单元的集成电路的第一原理图，并且生成限定集成电路的多个单元之间的预布置电互连的第二示意图，并且近似寄生电阻和寄生电容 的预布局互连。 然后，第一和第二原理图分别在第一和第二示意图中的对应的第一和第二端口组合。 操作还包括通过产生限定集成电路的多个单元之间的布局后互连的电路原理图来生成集成电路网表，并且近似寄生电阻和后布局互连的寄生电容。 然后将该电路示意图与其中的相应的第一和第二端口与第一示意图组合。 这些实施例还可以被配置为从集成电路的第一原理图生成布局示意图，并且生成在布局原理图中在多个单元之间延伸的布局后互连的寄生电阻和电容。 然后执行操作以在布局原理图中产生至少一个单元的内部的互连的寄生电阻和电容。

    FLOOR PLANK WITH ADHESIVE PORTION ABLE TO ADJUST THE POSITION
    3.
    发明申请
    FLOOR PLANK WITH ADHESIVE PORTION ABLE TO ADJUST THE POSITION 审中-公开
    具有粘合部分的地板可以调整位置

    公开(公告)号：US20090064623A1

    公开(公告)日：2009-03-12

    申请号：US12054966

    申请日：2008-03-25

    申请人： Jong-bae Lee

    发明人： Jong-bae Lee

    IPC分类号： E04F15/00

    CPC分类号： E04F15/02 ,  E04F2201/07 ,  E04F2203/06

    摘要： The present invention relates to a double-layered floor plank sheet having a non-adhesive portion, more particularly to a floor plank sheet enabling adjustment of position during installation. When the upper layer of a floor plank sheet is bonded to the lower layer of another floor plank sheet, a non-adhesive portion formed in part of an adhesive portion enables the adjustment of position.

    摘要翻译： 本发明涉及一种具有非粘合部分的双层地板板材，更具体地涉及一种能够在安装期间调整位置的地板板材。 当地板板的上层粘合到另一地板板的下层时，形成在粘合剂部分中的非粘合部分能够调节位置。

    Method and apparatus for verifying logic circuit
    5.
    发明申请
    Method and apparatus for verifying logic circuit 有权
    用于验证逻辑电路的方法和装置

    公开(公告)号：US20070168896A1

    公开(公告)日：2007-07-19

    申请号：US11649628

    申请日：2007-01-04

    申请人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

    发明人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5022

    摘要： A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

    摘要翻译： 一种用于验证逻辑电路的方法和装置，其能够更快的操作，被应用于逻辑门级或晶体管级电路设计，以及验证信号的定时和模拟信号特性。 逻辑电路验证方法包括波形文件生成阶段和逻辑电路验证阶段。 波形文件生成阶段使用逻辑电路的设计源文件生成包括逻辑电路的所有节点的波形的波形文件。 逻辑电路的验证阶段使用设计参考文件验证逻辑电路，该设计参考文件包括逻辑电路的所有节点和波形文件的理想操作。

    Method and apparatus for verifying logic circuit
    6.
    发明授权
    Method and apparatus for verifying logic circuit 有权
    用于验证逻辑电路的方法和装置

    公开(公告)号：US07913207B2

    公开(公告)日：2011-03-22

    申请号：US11649628

    申请日：2007-01-04

    申请人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

    发明人： Sang-ho Park ,  Jong-bae Lee ,  Moon-hyun Yoo ,  Ho Shim ,  Jin-won Kim

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： G06F17/5031 ,  G06F17/5022

    摘要： A method and an apparatus for verifying a logic circuit, capable of quicker operation, being applied to a logic gate-level or transistor-level circuit design, and verifying timing and analog signal characteristics of a signal. The logic circuit verification method includes a wave file generation stage and a logic circuit verification stage. The wave file generation stage generates a wave file that includes the waveforms of all nodes of the logic circuit using a design source file of the logic circuit. The stage of verification of the logic circuit verifies the logic circuit using a design reference file, which includes ideal operations of all the nodes of the logic circuit, and the wave file.

    摘要翻译： 一种用于验证逻辑电路的方法和装置，其能够更快的操作，被应用于逻辑门级或晶体管级电路设计，以及验证信号的定时和模拟信号特性。 逻辑电路验证方法包括波形文件生成阶段和逻辑电路验证阶段。 波形文件生成阶段使用逻辑电路的设计源文件生成包括逻辑电路的所有节点的波形的波形文件。 逻辑电路的验证阶段使用设计参考文件验证逻辑电路，该设计参考文件包括逻辑电路的所有节点和波形文件的理想操作。

    Headphone
    7.
    外观设计
    Headphone 有权

    公开(公告)号：USD585871S1

    公开(公告)日：2009-02-03

    申请号：US29300036

    申请日：2008-02-13

    申请人： Jong-bae Lee

    设计人： Jong-bae Lee

    Methods, Apparatus and Computer Program Products for Generating Selective Netlists that Include Interconnection Influences at Pre-Layout and Post-Layout Design Stages
    8.
    发明申请
    Methods, Apparatus and Computer Program Products for Generating Selective Netlists that Include Interconnection Influences at Pre-Layout and Post-Layout Design Stages 审中-公开
    用于生成选择性网络表的方法，设备和计算机程序产品，其中包括在布局前和布局后设计阶段的互连影响

    公开(公告)号：US20070094622A1

    公开(公告)日：2007-04-26

    申请号：US11563825

    申请日：2006-11-28

    申请人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

    发明人： Jong-bae Lee ,  Moon-hyun Yoo ,  Kyo-sun Kim ,  Jeong-min Choi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5068

    摘要： Operations for generating an integrated circuit netlist include generating a first schematic of an integrated circuit having a plurality of cells therein and generating a second schematic that defines pre-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the pre-layout interconnects. The first and second schematics are then combined at corresponding first and second ports within the first and second schematics, respectively. Operations also include generating an integrated circuit netlist by generating a circuit schematic that defines post-layout electrical interconnects between the plurality of cells of the integrated circuit and approximates parasitic resistances and parasitic capacitances of the post-layout interconnects. This circuit schematic is then combined with the first schematic at corresponding first and second ports therein. These embodiments may also be configured to generate a layout schematic from the first schematic of the integrated circuit and generate parasitic resistances and capacitances of the post-layout interconnects that extend between a plurality of cells in the layout schematic. Operations are then performed to generate parasitic resistances and capacitances of interconnects internal to at least one cell in the layout schematic.

    摘要翻译： 用于产生集成电路网表的操作包括生成其中具有多个单元的集成电路的第一原理图，并且生成限定集成电路的多个单元之间的预布置电互连的第二示意图，并且近似寄生电阻和寄生电容 的预布局互连。 然后，第一和第二原理图分别在第一和第二示意图中的对应的第一和第二端口组合。 操作还包括通过产生限定集成电路的多个单元之间的布局后互连的电路原理图来生成集成电路网表，并且近似寄生电阻和后布局互连的寄生电容。 然后将该电路示意图与其中的相应的第一和第二端口与第一示意图组合。 这些实施例还可以被配置为从集成电路的第一原理图生成布局示意图，并且生成在布局原理图中在多个单元之间延伸的布局后互连的寄生电阻和电容。 然后执行操作以在布局原理图中产生至少一个单元的内部的互连的寄生电阻和电容。

    Method and apparatus for designing fine pattern
    10.
    发明授权
    Method and apparatus for designing fine pattern 有权
    设计精细图案的方法和设备

    公开(公告)号：US07610574B2

    公开(公告)日：2009-10-27

    申请号：US11590399

    申请日：2006-10-31

    申请人： Jae-pil Shin ,  Young-ile Kim ,  Moon-hyun Yoo ,  Jong-bae Lee

    发明人： Jae-pil Shin ,  Young-ile Kim ,  Moon-hyun Yoo ,  Jong-bae Lee

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： Provided are a method and apparatus for designing a fine pattern that can be entirely transferred onto an object. The method includes reading the original data of a fine pattern for exposure. The fine pattern is divided into a first pattern not requiring revision and a second pattern requiring revision. The fine pattern is revised by forming an auxiliary pattern maintaining a first distance D1 from the second pattern. A fine pattern to be transferred onto a target object is estimated by running an emulation program including a first auxiliary pattern and a second auxiliary pattern. The estimated fine pattern is compared to the original data of the fine pattern for exposure, and the revised fine pattern is designated as a final fine pattern if there is no difference between the estimated fine pattern and the original data of the fine pattern for exposure.

    摘要翻译： 提供了一种用于设计可以完全转印到物体上的精细图案的方法和装置。 该方法包括读取用于曝光的精细图案的原始数据。 精细图案分为不需要修改的第一图案和需要修订的第二图案。 通过形成保持与第二图案的第一距离D1的辅助图案来修改精细图案。 通过运行包括第一辅助图案和第二辅助图案的仿真程序来估计要转印到目标对象上的精细图案。 将估计的精细图案与用于曝光的精细图案的原始数据进行比较，并且如果估计的精细图案与用于曝光的精细图案的原始数据之间没有差异，则将修改的精细图案指定为最终精细图案。