公开(公告)号：US20140017899A1

公开(公告)日：2014-01-16

申请号：US13976090

申请日：2011-12-29

Applicant: Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

Inventor： Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/0337

Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.

Abstract translation: 公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。 在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。 在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸 通过光刻工艺在衬底或其它合适的表面中形成的几何特征。 在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。

公开(公告)号：US20230207466A1

公开(公告)日：2023-06-29

申请号：US17561717

申请日：2021-12-24

Applicant: Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

Inventor： Leonard P. GULER ,  Jeffrey S. LEIB ,  Chanaka D. MUNASINGHE ,  Charles H. WALLACE ,  Tahir GHANI ,  Mohit K. HARAN

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/42392

Abstract: Embodiments include semiconductor devices. In an embodiment, a semiconductor device comprises a first non-planar transistor over a substrate and a second non-planar transistor over the substrate and parallel to the first non-planar transistor. In an embodiment, a gate structure is over the first non-planar transistor and the second non-planar transistor. In an embodiment, a power rail is between the first non-planar transistor and the second non-planar transistor. In an embodiment, a top surface of the power rail is below a top surface of a gate structure.

公开(公告)号：US09142421B2

公开(公告)日：2015-09-22

申请号：US13976090

申请日：2011-12-29

Applicant: Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

Inventor： Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

IPC: H01L21/469 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/3088 ,  H01L21/0337

Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.

Abstract translation: 公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。 在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。 在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸 通过光刻工艺在衬底或其它合适的表面中形成的几何特征。 在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。