公开(公告)号：US07759726B2

公开(公告)日：2010-07-20

申请号：US11179294

申请日：2005-07-12

申请人： Chao-Lun Yu ,  Chao-I Wu

发明人： Chao-Lun Yu ,  Chao-I Wu

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66833

摘要： The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, and each of the recess is interposed between two adjacent dielectric strips. The bit lines are respectively formed on the dielectric strips. The dielectrically stacking multi-layer comprising a charge-trapping layer is disposed on the bit lines and the recesses. The word lines are formed on the dielectrically stacking multi-layer and intersecting to the bit lines. When a voltage is applied to the bit lines, a plurality of inversion regions are respectively generated on the substrate.

摘要翻译： 本发明公开了一种非易失性存储器件及其制造方法。 非易失性存储器件的结构至少包括衬底，多个介质条，几个位线，介电层叠多层和多个字线。 基板有几个凹槽。 介质条形成在基板上，并且每个凹槽介于两个相邻的介质条之间。 位线分别形成在介质条上。 包含电荷捕获层的介电层叠多层设置在位线和凹部上。 字线形成在介电堆叠多层上并与位线相交。 当对位线施加电压时，在基板上分别产生多个反转区域。

公开(公告)号：US20070008777A1

公开(公告)日：2007-01-11

申请号：US11308777

申请日：2006-05-03

申请人： Ming-Hsiang Hsueh ,  Ming-Chang Kuo ,  Min-Ta Wu ,  Chao-Lun Yu

发明人： Ming-Hsiang Hsueh ,  Ming-Chang Kuo ,  Min-Ta Wu ,  Chao-Lun Yu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/10 ,  H01L29/42352 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

摘要： A non-volatile memory is described. The non-volatile memory includes a first source/drain region, a second source/drain region, a charge-trapping layer and a gate layer. The first source/drain region is disposed beside the top sidewall of a trench in a substrate. The second source/drain region is disposed in the substrate at the bottom of the trench. The gate layer is disposed in the trench and on the substrate. The charge-trapping layer is disposed between the gate layer and the substrate. A plurality of assisted charges is stored in one of the sides of the charge-trapping layer.

摘要翻译： 描述非易失性存储器。 非易失性存储器包括第一源极/漏极区域，第二源极/漏极区域，电荷俘获层和栅极层。 第一源极/漏极区域设置在衬底中的沟槽的顶侧壁旁边。 第二源极/漏极区域设置在沟槽底部的衬底中。 栅极层设置在沟槽和衬底上。 电荷捕获层设置在栅极层和衬底之间。 多个辅助电荷存储在电荷捕获层的一侧中。

公开(公告)号：US07292478B2

公开(公告)日：2007-11-06

申请号：US11222708

申请日：2005-09-08

申请人： Chao-Lun Yu ,  Chao-I Wu

发明人： Chao-Lun Yu ,  Chao-I Wu

IPC分类号： G11C16/04

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42352

摘要： A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.

摘要翻译： 描述了非易失性存储单元，包括其中具有沟槽的半导体衬底，沟槽中的电荷俘获层，设置在沟槽中的栅极和至少由电荷俘获层与衬底分离的栅极，以及S / 在沟槽旁边的衬底中的D区域。 栅极包括p掺杂的半导体材料，使得存储单元特别适合于通过从栅极注入空穴进行擦除。

公开(公告)号：US20070063268A1

公开(公告)日：2007-03-22

申请号：US11222708

申请日：2005-09-08

申请人： Chao-Lun Yu ,  Chao-I Wu

发明人： Chao-Lun Yu ,  Chao-I Wu

IPC分类号： H01L29/94

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42352

摘要： A non-volatile memory cell is described, including a semiconductor substrate with a trench therein, a charge-trapping layer in the trench, a gate disposed in the trench and separated from the substrate by at least the charge-trapping layer, and S/D regions in the substrate beside the trench. The gate includes a p-doped semiconductor material, so that the memory cell is particularly suitable to erase through hole injection from the gate.

摘要翻译： 描述了非易失性存储单元，包括其中具有沟槽的半导体衬底，沟槽中的电荷俘获层，设置在沟槽中的栅极和至少由电荷俘获层与衬底分离的栅极，以及S / 在沟槽旁边的衬底中的D区域。 栅极包括p掺杂的半导体材料，使得存储单元特别适合于通过从栅极注入空穴进行擦除。

公开(公告)号：US20070012993A1

公开(公告)日：2007-01-18

申请号：US11179294

申请日：2005-07-12

申请人： Chao-Lun Yu ,  Chao-I Wu

发明人： Chao-Lun Yu ,  Chao-I Wu

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66833

摘要： The present invention disclosed a non-volatile memory device and fabricating method thereof. The structure of non-volatile memory device at least comprises a substrate, several dielectric strips, several bit lines, a dielectrically stacking multi-layer, and several word lines. The substrate has several recesses. The dielectric strips are formed on the substrate, and each of the recess is interposed between two adjacent dielectric strips. The bit lines are respectively formed on the dielectric strips. The dielectrically stacking multi-layer comprising a charge-trapping layer is disposed on the bit lines and the recesses. The word lines are formed on the dielectrically stacking multi-layer and intersecting to the bit lines. When a voltage is applied to the bit lines, a plurality of inversion regions are respectively generated on the substrate.

摘要翻译： 本发明公开了一种非易失性存储器件及其制造方法。 非易失性存储器件的结构至少包括衬底，多个介质条，几个位线，介电层叠多层和多个字线。 基板有几个凹槽。 介质条形成在基板上，并且每个凹槽介于两个相邻的介质条之间。 位线分别形成在介质条上。 包含电荷捕获层的介电层叠多层设置在位线和凹部上。 字线形成在介电堆叠多层上并与位线相交。 当对位线施加电压时，在基板上分别产生多个反转区域。