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11 条记录 (耗时 0.02 秒)

    Parameterizable queued memory access system
    1.
    发明授权
    Parameterizable queued memory access system 有权
    可参数化的排队内存访问系统

    公开(公告)号：US06735677B1

    公开(公告)日：2004-05-11

    申请号：US09847848

    申请日：2001-04-30

    申请人： Charles H. Stewart

    发明人： Charles H. Stewart

    IPC分类号： G06F1318

    CPC分类号： G06F13/1642

    摘要： A unique memory access system and method to handle memory access requests to a memory shared by multiple independent data access devices (“IDADs”). More particularly, the present invention relates to a method and system that allows IDADs to efficiently execute memory access requests without having to wait for the shared memory to be available. In addition, the IDADs do not have to be designed to observe the specific memory protocol. The memory access requests from the IDADs are accepted by access request logic which then queues the requests. Memory access logic then executes the requests from the queue when the shared memory is available. The memory access logic places data obtained from read requests in a read buffer for the IDADs to access when convenient.

    摘要翻译： 独特的存储器访问系统和方法，用于处理由多个独立数据访问设备（“IDAD”）共享的存储器的存储器访问请求。 更具体地说，本发明涉及允许IDAD有效地执行存储器访问请求而不必等待共享存储器可用的方法和系统。 此外，IDAD不必设计为观察特定的存储器协议。 来自IDAD的存储器访问请求被访问请求逻辑接受，然后对请求进行排队。 当共享存储器可用时，存储器访问逻辑然后执行来自队列的请求。 存储器访问逻辑将从读取请求获得的数据放置在用于IDAD的读取缓冲器中以便于访问。

    Bridge for coupling digital signal processor to on-chip bus as master
    2.
    发明授权
    Bridge for coupling digital signal processor to on-chip bus as master 有权
    将数字信号处理器耦合到片上总线作为主机的桥

    公开(公告)号：US06687773B1

    公开(公告)日：2004-02-03

    申请号：US09847849

    申请日：2001-04-30

    申请人： Charles H. Stewart ,  Keith D. Dang

    发明人： Charles H. Stewart ,  Keith D. Dang

    IPC分类号： G06F1338

    CPC分类号： G06F13/4027

    摘要： A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

    摘要翻译： 用于将DSP连接到作为总线上的主机的ASIC片上总线的桥。 该桥包括DSP指令单元主接口和DSP数据单元主接口，用于将DSP指令单元和数据单元外部信号转换为总线协议信号。 提供仲裁器以接收来自两个DSP接口的信号，并选择性地将信号传递到将信号耦合到片上总线的通用总线主机。 提供同步单元以确保ASIC和DSP的不同时钟频率之间的正时钟转换的对准，并根据需要缓冲信号。 通用总线主机完全符合总线协议，将仲裁器和同步单元的信号耦合到ASIC总线。

    System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline
    4.
    发明授权
    System and method for extracting instruction boundaries in a fetched cacheline, given an arbitrary offset within the cacheline 有权
    在提取的高速缓存行中提取指令边界的系统和方法，给出了高速缓存行内的任意偏移量

    公开(公告)号：US06961844B1

    公开(公告)日：2005-11-01

    申请号：US09972404

    申请日：2001-10-05

    申请人： Charles H. Stewart ,  Asheesh Kashyap

    发明人： Charles H. Stewart ,  Asheesh Kashyap

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30152 ,  G06F9/382

    摘要： A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.

    摘要翻译： 呈现系统和方法用于在从存储器取出的指令块内进行预解码（即，确定）可变长度指令的地址边界。 指令块表示存储器中的连续地址的内容，并且响应于微处理器对块内的特定指令的请求而获取。 在预解码之后，存在于块中的指令被放置在高速缓存中以供微处理器执行。 传统的指令预解码方法仅适用于从请求指令的地址以外的地址取出的指令。 因此，块中的剩余指令不被使用。 本文公开的系统和方法允许对指令块的后向预解码，其中还可以确定从请求的指令之前的地址获取的指令的地址边界。 该功能可以更有效地使用缓存。

    Integrated circuit containing multiple digital signal processors
    5.
    发明授权
    Integrated circuit containing multiple digital signal processors 有权
    包含多个数字信号处理器的集成电路

    公开(公告)号：US06959376B1

    公开(公告)日：2005-10-25

    申请号：US09975677

    申请日：2001-10-11

    申请人： Mark Boike ,  Alan Phan ,  Keith Dang ,  Charles H. Stewart

    发明人： Mark Boike ,  Alan Phan ,  Keith Dang ,  Charles H. Stewart

    IPC分类号： G06F15/16 ,  G06F15/80

    CPC分类号： G06F15/8007

    摘要： The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

    摘要翻译： 本发明是一种包含多个数字信号处理器（DSP）的集成电路。 单个主机处理器接口也放置在芯片上，以将多个DSP连接到主机。 为每个DSP提供单独的直接存储器访问（DMA）单元，以促进数据到每个DSP的数据存储器和从数据存储器流出。 每个DSP还包括一个指令存储器。

    Method for exploring for hydrocarbons utilizing three dimensional modeling of thermal anomalies
    6.
    发明授权
    Method for exploring for hydrocarbons utilizing three dimensional modeling of thermal anomalies 失效
    利用热异常三维建模探索碳氢化合物的方法

    公开(公告)号：US5321612A

    公开(公告)日：1994-06-14

    申请号：US661902

    申请日：1991-02-26

    申请人： Charles H. Stewart

    发明人： Charles H. Stewart

    IPC分类号： G01V9/00 ,  G01V1/00

    CPC分类号： G01V9/005

    摘要： A method for exploring and finding a subterranean hydrocarbon reservoir by modeling of temperature and/or thermal anomalies within a geologic volume of the earth's crust. The geologic volume is subdivided into a plurality of laterally disposed and aligned, and vertically disposed and aligned, volumetric cells. Geologic properties are assigned for each of the volumetric cells, and a normal gradient temperature is determined and generated for the geologic volume. An x, y, z temperature is assigned for each volumetric cell based on the normal gradient temperature of the geologic volume. A hypothetical hydrocarbon reservoir is disposed in the geologic volume by varying the geologic properties of some of the plurality of volumetric cells; and a true x, y, z temperature is computed for each volumetric cell caused by the hypothetical hydrocarbon reservoir. A true hydrocarbon reservoir in the geologic volume is determined from the true x, y, z temperature of each volumetric cell.

    摘要翻译： 通过对地壳地质体积内的温度和/或热异常进行建模来探索和找到地下油气藏的方法。 地质体积被细分为多个横向设置和排列并且垂直设置和对准的体积细胞。 为每个体积细胞分配地质属性，并为地质体积确定和生成正常梯度温度。 基于地质体积的正常梯度温度，为每个体积细胞分配x，y，z温度。 通过改变多个体积细胞中的一些容积细胞的地质特性，在地质体积中设置假设的烃储层; 并且对于由假设的烃储层引起的每个体积池计算真实的x，y，z温度。 地质体积中的真实碳氢化合物储层由每个体积细胞的真实x，y，z温度确定。

    Bridge for coupling digital signal processor to on-chip bus as slave
    9.
    发明授权
    Bridge for coupling digital signal processor to on-chip bus as slave 有权
    将数字信号处理器耦合到片上总线作为从机的桥

    公开(公告)号：US06789153B1

    公开(公告)日：2004-09-07

    申请号：US09847850

    申请日：2001-04-30

    申请人： Charles H. Stewart

    发明人： Charles H. Stewart

    IPC分类号： G06F1300

    CPC分类号： G06F13/4031

    摘要： A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.

    摘要翻译： 用于将DSP连接到作为从站的ASIC片上总线的桥。 该桥耦合在DSP内部存储器直接存储器接口和诸如AMBA AHB之类的片上总线之间的信号。 该桥包括通用从模块，其提供与片上总线协议中的片上总线的直接连接。 它还包括连接到DSP存储器接口的从属引擎，以控制与存储器的读写事务。 通用从机和从引擎通过脉冲种植器和脉冲剃须刀耦合，以允许发动机以DSP时钟频率工作，而通用从机以通常较慢的片上总线频率运行。 该桥允许ASIC中的主器件与DSP内部存储器执行读写操作。