公开(公告)号：US06687773B1

公开(公告)日：2004-02-03

申请号：US09847849

申请日：2001-04-30

申请人： Charles H. Stewart ,  Keith D. Dang

发明人： Charles H. Stewart ,  Keith D. Dang

IPC分类号： G06F1338

CPC分类号： G06F13/4027

摘要： A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

摘要翻译： 用于将DSP连接到作为总线上的主机的ASIC片上总线的桥。 该桥包括DSP指令单元主接口和DSP数据单元主接口，用于将DSP指令单元和数据单元外部信号转换为总线协议信号。 提供仲裁器以接收来自两个DSP接口的信号，并选择性地将信号传递到将信号耦合到片上总线的通用总线主机。 提供同步单元以确保ASIC和DSP的不同时钟频率之间的正时钟转换的对准，并根据需要缓冲信号。 通用总线主机完全符合总线协议，将仲裁器和同步单元的信号耦合到ASIC总线。

公开(公告)号：US06694410B1

公开(公告)日：2004-02-17

申请号：US09845909

申请日：2001-04-30

申请人： Keith D. Dang

发明人： Keith D. Dang

IPC分类号： G06F1200

CPC分类号： G06F13/405

摘要： A system for receiving transaction requests from a plurality of data access devices, coupling them to a shared memory having an input queue and identifying each completed transaction with the requesting device. The system includes a controller for receiving the requests and selectively coupling them to a shared memory input queue. A first-in-first-out identification memory stores a requesting device identifier which the controller uses to route transaction completion control signals and data back to the device which requested the transaction.

摘要翻译： 一种用于从多个数据访问设备接收事务请求的系统，将它们耦合到具有输入队列的共享存储器，并且与请求设备识别每个完成的事务。 该系统包括用于接收请求并选择性地将它们耦合到共享存储器输入队列的控制器。 先进先出识别存储器存储控制器用于将事务完成控制信号和数据路由到请求事务的设备的请求设备标识符。

公开(公告)号：US5416731A

公开(公告)日：1995-05-16

申请号：US292445

申请日：1994-08-18

申请人： Keith D. Dang ,  Donald C. Anderson

发明人： Keith D. Dang ,  Donald C. Anderson

IPC分类号： G06F5/01

CPC分类号： G06F5/015

摘要： A high-speed barrel shifter (20) includes a shifter array (25) having a matrix of transistors (40) located at intersections of rows and columns of the matrix (40). The rows and columns alternately function as source and destination terminals. A fill portion (48) fills either a predetermined value or a data-dependent value such as a sign bit into vacated bit positions along rows in a bottom left portion (42). Thus the barrel shifter (20) can perform a data-dependent fill instruction within the shifter array (25) and avoids extra clock cycles associated with post-array processing. In one embodiment, an isolation portion (44, 45) separates a top right portion (41) of the matrix (40) from the bottom left portion (42) along a diagonal (43). The isolation portion (44, 45) isolates transistors in the bottom left portion (42), which are associated with rotates and fills, from transistors in the top right portion (41), which are associated with shifts, according to the direction of the shift.

摘要翻译： 高速桶形移位器（20）包括具有位于矩阵（40）的行和列的交叉处的晶体管（40）的矩阵的移位器阵列（25）。 行和列交替作为源和目标终端。 填充部分（48）将预定值或诸如符号位的数据相关值填充到沿着左下部分（42）中的行的空位位置。 因此，桶形移位器（20）可以在移位器阵列（25）内执行与数据相关的填充指令，并避免与后阵列处理相关联的额外的时钟周期。 在一个实施例中，隔离部分（44,45）沿着对角线（43）将矩阵（40）的右上部分（41）与左下部分（42）分开。 隔离部分（44,45）根据与所述顶部右侧部分（41）的方向相关联的与所述右上部分（41）相关联的晶体管，将与所述左下部分（42）相关的晶体管与所述右上部分 转移。

公开(公告)号：US07167939B2

公开(公告)日：2007-01-23

申请号：US10911798

申请日：2004-08-05

申请人： Hung T. Nguyen ,  Keith D. Dang

发明人： Hung T. Nguyen ,  Keith D. Dang

IPC分类号： G06F13/368 ,  G06F3/00 ,  G06F13/14 ,  G06F11/00

CPC分类号： G06F13/4004

摘要： A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transactions, initiated by a system device coupled to the global bus, that require access to a local device coupled to the local bus and a global bus adapter for handling transactions, initiated by a local device coupled to the local bus, that require access to a system device coupled to the system bus. The local bus adapter is further configured to issue signals which prevent the global bus adapter from handling transactions initiated by local devices coupled to the local bus while transactions initiated by system devices coupled to the global bus are on-going.

摘要翻译： 具有分层总线结构的计算机系统，其允许本地总线与其全局总线的去耦合。 通过使用异步系统总线适配器来实现本地总线的去耦，该异步系统总线适配器包括用于处理由耦合到全局总线的系统设备启动的事务的本地总线适配器，其需要访问耦合到本地总线的本地设备和 用于处理由耦合到本地总线的本地设备启动的事务的全局总线适配器，其需要访问耦合到系统总线的系统设备。 本地总线适配器还被配置为发出信号，其阻止全局总线适配器处理由耦合到本地总线的本地设备发起的事务，同时由耦合到全局总线的系统设备发起的事务正在进行。

公开(公告)号：US5321640A

公开(公告)日：1994-06-14

申请号：US982521

申请日：1992-11-27

申请人： Donald C. Anderson ,  Keith D. Dang

发明人： Donald C. Anderson ,  Keith D. Dang

IPC分类号： G06F7/74 ,  G06F7/00

CPC分类号： G06F7/74

摘要： A priority encoder (12) has a most significant bit circuitry (18), a first less significant bit circuitry (20) and a second less significant bit circuitry (22). The priority encoder detects a leading one within a plurality of data bits. Each data bit is associated with a different one of a plurality of input signals. The most significant bit circuitry is coupled to a first one of the input signals and generates a first output signal and a parallel blocking signal. Both of the first output signal and the parallel blocking signal are representative in a first logic state of a leading one associated with the first signal. The first less significant bit cell is coupled to a second one of the input signals and to the parallel blocking signal. The first less significant bit cell generates a second output signal and a less significant carry signal. Both the second output signal and the less significant carry signal are representative in a first logic state of a leading one associated with the second input signal. The second less significant bit cell is coupled to a third one of the input signals, to the parallel blocking signal and to the less significant carry signal. The second less significant bit cell generates a third output signal representative in a first logic state of a leading one associated with the third input signal.

摘要翻译： 优先级编码器（12）具有最高有效位电路（18），第一较低有效位电路（20）和第二较低有效位电路（22）。 优先编码器检测多个数据位中的前导码。 每个数据位与多个输入信号中的不同的一个相关联。 最高有效位电路耦合到输入信号中的第一个，并产生第一输出信号和并行阻塞信号。 第一输出信号和并联阻塞信号两者都代表与第一信号相关联的前导信号的第一逻辑状态。 第一较低有效位单元耦合到输入信号中的第二个和并行阻塞信号。 第一较低有效位单元产生第二输出信号和较不重要的进位信号。 第二输出信号和较低有效进位信号都代表与第二输入信号相关联的前导信号的第一逻辑状态。 第二较低有效位单元耦合到输入信号中的第三个，并联到并行阻塞信号和较不重要的进位信号。 第二较低有效位单元产生代表与第三输入信号相关联的前导的第一逻辑状态的第三输出信号。