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9 条记录 (耗时 0.016 秒)

    Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
    2.
    发明授权
    Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) 失效
    在一组协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环再现仿真的方法和基础设施，

    公开(公告)号：US08640070B2

    公开(公告)日：2014-01-28

    申请号：US12941834

    申请日：2010-11-08

    申请人： Sameh W Asaad ,  Ralph E Bellofatto ,  Bernard Brezzo ,  Charles L Haymes ,  Mohit Kapur ,  Benjamin D Parker ,  Thomas Roewer ,  Jose A Tierno

    发明人： Sameh W Asaad ,  Ralph E Bellofatto ,  Bernard Brezzo ,  Charles L Haymes ,  Mohit Kapur ,  Benjamin D Parker ,  Thomas Roewer ,  Jose A Tierno

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  H03K19/17736

    摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

    摘要翻译： 多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。 控制模块耦合到多个目标现场可编程门阵列。 平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。 控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。 多个本地时钟控制状态机驻留在目标现场可编程门阵列中。 本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。 多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。 还提供了一种方法。

    Format converter
    3.
    发明授权
    Format converter 失效
    格式转换器

    公开(公告)号：US06429794B1

    公开(公告)日：2002-08-06

    申请号：US09609048

    申请日：2000-06-30

    申请人： Albert X. Widmer ,  Charles L. Haymes ,  Benjamin D. Parker

    发明人： Albert X. Widmer ,  Charles L. Haymes ,  Benjamin D. Parker

    IPC分类号： H03M900

    CPC分类号： H03M9/00

    摘要： A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine which controls the operating mode and to which it delivers status information. The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.

    摘要翻译： 格式转换器，其中数据输入是16位宽的接口。 该电路找到66位编码块边界。 在一个实施例中，电路以对准格式在输出处呈现66位数据块。 该电路依赖于来自状态机的控制输入，该状态机控制操作模式并传送状态信息。 两种主要操作模式是“正常数据”模式或66位块边界的“寻线”模式。

    System and method for connection of multiple protocol terminals
    4.
    发明授权
    System and method for connection of multiple protocol terminals 失效
    用于连接多个协议终端的系统和方法

    公开(公告)号：US5568525A

    公开(公告)日：1996-10-22

    申请号：US109185

    申请日：1993-08-19

    申请人： Richard H. J. de Nijs ,  Charles L. Haymes ,  Dale T. Ulmer

    发明人： Richard H. J. de Nijs ,  Charles L. Haymes ,  Dale T. Ulmer

    IPC分类号： G06F13/00 ,  H04L29/06 ,  H04L7/00

    CPC分类号： H04L29/06

    摘要： A network port configurator device for automatically configuring a system having network workstations and corresponding network equipment of various physical protocols. The network port configurator comprises a plurality of input and output ports for receiving physical wiring to which the workstations and network equipment are attached. Detection circuitry attached to the input and output ports determine the physical protocol of the attached workstations and network equipment by determining a characteristic of the attached equipment. Examples of identifying characteristics include a characteristic impedance, a characteristic voltage, and a characteristic cable identification of the workstation. Logic circuitry uses this information to control a circuit switching mechanism that connects the input ports to the output ports.

    摘要翻译： 一种用于自动配置具有各种物理协议的网络工作站和相应网络设备的系统的网络端口配置器设备。 网络端口配置器包括多个输入和输出端口，用于接收工作站和网络设备所连接的物理布线。 连接到输入和输出端口的检测电路通过确定连接的设备的特性来确定连接的工作站和网络设备的物理协议。 识别特性的示例包括工作站的特征阻抗，特征电压和特征电缆识别。 逻辑电路使用该信息来控制将输入端口连接到输出端口的电路交换机制。

    Low-cost radio frequency (RF) link for point-to-point data transfer
    7.
    发明授权
    Low-cost radio frequency (RF) link for point-to-point data transfer 失效
    用于点对点数据传输的低成本射频（RF）链路

    公开(公告)号：US06754259B1

    公开(公告)日：2004-06-22

    申请号：US09438058

    申请日：1999-11-10

    申请人： Brian Paul Gaucher ,  Charles L. Haymes ,  Modest M. Oprysko ,  Mark B. Ritter

    发明人： Brian Paul Gaucher ,  Charles L. Haymes ,  Modest M. Oprysko ,  Mark B. Ritter

    IPC分类号： H04B138

    CPC分类号： H04W88/02

    摘要： An apparatus for data transfer using radio frequency (RF) energy, includes a first software application that sources and links the data transfer, a second software application for controlling a communications hardware for the data transfer, a hardware device for formatting the data and gaining access to a media, and a physical layer interface hardware, coupled to selectively receive a signal representing the data from the hardware device and to provide an output to the hardware device, for sending and receiving a radio frequency communication. The second software application for controlling the communications hardware uses a target data transmission media of infrared light.

    摘要翻译： 一种用于使用射频（RF）能量进行数据传输的装置，包括：源和连接数据传输的第一软件应用程序，用于控制用于数据传送的通信硬件的第二软件应用程序，用于格式化数据和获得访问的硬件设备 耦合到介质和物理层接口硬件，耦合到有选择地从硬件设备接收表示数据的信号并向硬件设备提供输出以发送和接收射频通信。 用于控制通信硬件的第二软件应用使用红外光的目标数据传输介质。

    METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs)
    8.
    发明申请
    METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) 失效
    方法和基础设施，用于在协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环复制仿真

    公开(公告)号：US20120117413A1

    公开(公告)日：2012-05-10

    申请号：US12941834

    申请日：2010-11-08

    申请人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

    发明人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

    IPC分类号： G06F1/06 ,  G06F1/04

    CPC分类号： G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  H03K19/17736

    摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

    摘要翻译： 多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。 控制模块耦合到多个目标现场可编程门阵列。 平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。 控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。 多个本地时钟控制状态机驻留在目标现场可编程门阵列中。 本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。 多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。 还提供了一种方法。