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    Testing and operating a multiprocessor chip with processor redundancy
    1.
    发明授权
    Testing and operating a multiprocessor chip with processor redundancy 有权
    测试和操作具有处理器冗余的多处理器芯片

    公开(公告)号：US08868975B2

    公开(公告)日：2014-10-21

    申请号：US13196459

    申请日：2011-08-02

    申请人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    发明人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    IPC分类号： G06F11/00 ,  G06F11/22 ,  G06F11/20

    CPC分类号： G06F11/2242 ,  G06F11/202

    摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

    摘要翻译： 一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。 第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。 第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。 如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。 响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。 片上逻辑根据所选的物理到逻辑映射配置处理器内核。

    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan
    2.
    发明授权
    Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan 失效
    通过同步时钟停止和扫描来调试集成电路芯片的方法和装置

    公开(公告)号：US08140925B2

    公开(公告)日：2012-03-20

    申请号：US11768791

    申请日：2007-06-26

    申请人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    发明人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    IPC分类号： G01R31/28 ,  G06F1/12

    CPC分类号： G06F11/2236

    摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

    摘要翻译： 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

    METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs)
    3.
    发明申请
    METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) 失效
    方法和基础设施，用于在协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环复制仿真

    公开(公告)号：US20120117413A1

    公开(公告)日：2012-05-10

    申请号：US12941834

    申请日：2010-11-08

    申请人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

    发明人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

    IPC分类号： G06F1/06 ,  G06F1/04

    CPC分类号： G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  H03K19/17736

    摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

    摘要翻译： 多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。 控制模块耦合到多个目标现场可编程门阵列。 平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。 控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。 多个本地时钟控制状态机驻留在目标现场可编程门阵列中。 本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。 多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。 还提供了一种方法。

    METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN
    6.
    发明申请
    METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN 失效
    通过同步时钟停止和扫描来调试集成电路芯片的方法和设备

    公开(公告)号：US20090006894A1

    公开(公告)日：2009-01-01

    申请号：US11768791

    申请日：2007-06-26

    申请人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    发明人： Ralph E. Bellofatto ,  Matthew R. Ellavsky ,  Alan G. Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Rudolf A. Haring ,  Lance G. Hehenberger ,  Martin Ohmacht

    IPC分类号： G06F11/00

    CPC分类号： G06F11/2236

    摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

    摘要翻译： 一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。 该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。 该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

    Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
    9.
    发明授权
    Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs) 失效
    在一组协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环再现仿真的方法和基础设施，

    公开(公告)号：US08640070B2

    公开(公告)日：2014-01-28

    申请号：US12941834

    申请日：2010-11-08

    申请人： Sameh W Asaad ,  Ralph E Bellofatto ,  Bernard Brezzo ,  Charles L Haymes ,  Mohit Kapur ,  Benjamin D Parker ,  Thomas Roewer ,  Jose A Tierno

    发明人： Sameh W Asaad ,  Ralph E Bellofatto ,  Bernard Brezzo ,  Charles L Haymes ,  Mohit Kapur ,  Benjamin D Parker ,  Thomas Roewer ,  Jose A Tierno

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  H03K19/17736

    摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

    摘要翻译： 多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。 控制模块耦合到多个目标现场可编程门阵列。 平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。 控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。 多个本地时钟控制状态机驻留在目标现场可编程门阵列中。 本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。 多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。 还提供了一种方法。

    TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY
    10.
    发明申请
    TESTING AND OPERATING A MULTIPROCESSOR CHIP WITH PROCESSOR REDUNDANCY 有权
    测试和操作具有处理器冗余的多处理器芯片

    公开(公告)号：US20130031418A1

    公开(公告)日：2013-01-31

    申请号：US13196459

    申请日：2011-08-02

    申请人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    发明人： Ralph E. Bellofatto ,  Steven M. Douskey ,  Rudolf A. Haring ,  Moyra K. McManus ,  Martin Ohmacht ,  Dietmar Schmunkamp ,  Krishnan Sugavanam ,  Bryan J. Weatherford

    IPC分类号： G06F11/28

    CPC分类号： G06F11/2242 ,  G06F11/202

    摘要： A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

    摘要翻译： 一种用于提高包括主处理器核心和一个或多个冗余处理器核心的多处理器半导体芯片的产率的系统和方法。 第一个测试人员对一个或多个处理器内核进行第一次测试，并在片上非易失性存储器中对第一次测试的结果进行编码。 第二个测试者对处理器核进行第二次测试，并将外部非易失性存储设备的第二次测试结果进行编码。 如果处理器核心故障第二次测试，则设置多路复用器的覆盖位。 响应于覆盖位，多路复用器根据以下之一选择处理器ID的物理到逻辑映射：存储器件中的编码结果或外部存储器件中的编码结果。 片上逻辑根据所选的物理到逻辑映射配置处理器内核。