公开(公告)号：US20120117413A1

公开(公告)日：2012-05-10

申请号：US12941834

申请日：2010-11-08

申请人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

发明人： Sameh W. Asaad ,  Ralph E. Bellofatto ,  Bernard Brezzo ,  Charles L. Haymes ,  Mohit Kapur ,  Benjamin D. Parker ,  Thomas Roewer ,  Jose A. Tierno

IPC分类号： G06F1/06 ,  G06F1/04

CPC分类号： G06F1/10 ,  G06F1/06 ,  G06F17/5027 ,  H03K19/17736

摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

摘要翻译： 多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。 控制模块耦合到多个目标现场可编程门阵列。 平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。 控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。 多个本地时钟控制状态机驻留在目标现场可编程门阵列中。 本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。 多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。 还提供了一种方法。

公开(公告)号：US09286423B2

公开(公告)日：2016-03-15

申请号：US13435707

申请日：2012-03-30

申请人： Sameh W. Asaad ,  Mohit Kapur

发明人： Sameh W. Asaad ,  Mohit Kapur

IPC分类号： G06F17/50

CPC分类号： G01R31/31703 ,  G01R31/2851 ,  G01R31/31727 ,  G01R31/3177 ,  G06F17/5027

摘要： A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

摘要翻译： 公开了一种使用现场可编程门阵列（FPGA）来模拟待测器件（DUT）的操作的方法，系统和计算机程序产品。 DUT包括具有多个输入端口的设备存储器，并且FPGA与具有第二数量的输入端口的目标存储器相关联，第二数量小于第一数量。 在一个实施例中，给定的一组输入以频率Fd和定义的时间周期被施加到设备存储器，并且给定的一组输入以频率Ft被施加到目标存储器。 Ft大于Fd，并且在设备存储器和目标存储器之间保持循环精度。 在一个实施例中，通过将DUT存储器接口协议与目标存储器存储阵列分离来创建DUT存储器的周期精确模型。

公开(公告)号：US20080215854A1

公开(公告)日：2008-09-04

申请号：US12121542

申请日：2008-05-15

申请人： Sameh W. Asaad ,  Richard Gerard Hofmann

发明人： Sameh W. Asaad ,  Richard Gerard Hofmann

IPC分类号： G06F9/312

CPC分类号： G06F9/3885 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/3897

摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

摘要翻译： 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括 一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除，指令被执行。

公开(公告)号：US06754761B1

公开(公告)日：2004-06-22

申请号：US09633856

申请日：2000-08-07

申请人： Sameh W. Asaad ,  Kevin W. Warren

发明人： Sameh W. Asaad ,  Kevin W. Warren

IPC分类号： G06F1336

CPC分类号： G06F13/4027

摘要： A method of (and system for) of transporting a sideband signal through a physical layer of an extended bridge, includes on a first node of the extended bridge, providing an interface to a sideband component coupled to a side of the extended bridge, encoding a first data stream being output from the sideband component with a unique header to identify the data output from the sideband component, and multiplexing the first data stream from the sideband component with a second data stream from a principal signal port, and outputting the multiplexed first and second data streams to another node of the extended bridge.

摘要翻译： 通过扩展桥的物理层传送边带信号的方法（和系统）包括在扩展桥的第一节点上，提供与耦合到扩展桥的一侧的边带分量的接口，编码 第一数据流是从边带分量输出的唯一标题，以识别从边带分量输出的数据，并且从边带分量与来自主信号端口的第二数据流多路复用第一数据流，并且首先输出多路复用 第二数据流到扩展桥的另一个节点。

公开(公告)号：US07523449B2

公开(公告)日：2009-04-21

申请号：US11508714

申请日：2006-08-23

申请人： Sameh W. Asaad ,  Richard Gerard Hofmann

发明人： Sameh W. Asaad ,  Richard Gerard Hofmann

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F15/00 ,  G06F7/38 ,  G06F12/00

CPC分类号： G06F9/3885 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/3897

摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

摘要翻译： 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括 一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除，指令被执行。

公开(公告)号：US07167971B2

公开(公告)日：2007-01-23

申请号：US10881146

申请日：2004-06-30

申请人： Sameh W. Asaad ,  Richard Gerard Hofmann

发明人： Sameh W. Asaad ,  Richard Gerard Hofmann

IPC分类号： G06F9/30 ,  G06F9/00

CPC分类号： G06F9/3885 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/3897

摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

摘要翻译： 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括 一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除，指令被执行。

公开(公告)号：US08805850B2

公开(公告)日：2014-08-12

申请号：US13478507

申请日：2012-05-23

申请人： Bharat Sukhwani ,  Sameh W. Asaad ,  Hong Min ,  Mathew S. Thoennes ,  Gong Su

发明人： Bharat Sukhwani ,  Sameh W. Asaad ,  Hong Min ,  Mathew S. Thoennes ,  Gong Su

IPC分类号： G06F17/30

CPC分类号： G06F17/30498

摘要： Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator.

摘要翻译： 为硬件加速的关系连接提供了技术。 通过硬件加速器处理包括一行或多行的第一表。 在第一表的一行或多行中的至少一行中的至少一个连接列被散列以在至少一个位向量中设置至少一个位。 通过硬件加速器处理包括一行或多行的第二表。 第二表的一行或多行中的至少一行中的至少一个连接列被散列以生成至少一个散列值。 使用至少一个哈希值来探测至少一个比特向量。 响应于探测步骤构建连接的行。 行结构步骤在硬件加速器中执行。

公开(公告)号：US20130318067A1

公开(公告)日：2013-11-28

申请号：US13478507

申请日：2012-05-23

申请人： Bharat Sukhwani ,  Sameh W. Asaad ,  Hong Min ,  Matthew S. Thoennes ,  Gong Su

发明人： Bharat Sukhwani ,  Sameh W. Asaad ,  Hong Min ,  Matthew S. Thoennes ,  Gong Su

IPC分类号： G06F17/30

CPC分类号： G06F17/30498

摘要： Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator.

摘要翻译： 为硬件加速的关系连接提供了技术。 通过硬件加速器处理包括一行或多行的第一表。 在第一表的一行或多行中的至少一行中的至少一个连接列被散列以在至少一个位向量中设置至少一个位。 通过硬件加速器处理包括一行或多行的第二表。 第二表的一行或多行中的至少一行中的至少一个连接列被散列以生成至少一个散列值。 使用至少一个哈希值来探测至少一个比特向量。 响应于探测步骤构建连接的行。 行结构步骤在硬件加速器中执行。

公开(公告)号：US07130963B2

公开(公告)日：2006-10-31

申请号：US10620734

申请日：2003-07-16

申请人： Sameh W. Asaad ,  Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

发明人： Sameh W. Asaad ,  Jaime H. Moreno ,  Jude A. Rivers ,  John-David Wellman

IPC分类号： G06F12/00

CPC分类号： G06F9/381

摘要： A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.

摘要翻译： 一种用于具有处理器的计算设备中的指令存储器存储和处理的系统，所述系统基于向后分支控制信息，并且包括动态循环缓冲器（DLB），其是被组织为直接映射结构的无标记数据阵列; DLB控制器具有划分为多​​个存储体的主存储器单元，用于控制指令存储器系统的状态并接受程序计数器地址作为输入，DLB控制器输出不同的信号。 该系统还包括位于计算设备的存储器中的地址寄存器，它是用于程序计数器地址的分段寄存器和执行处理器时钟的两个周期的指令获取处理; 以及用于作为程序计数器地址解码器接受程序计数器地址并输出用于选择主存储器单元中的存储体的存储体使能信号的存储体选择单元和在所选择的存储体内的存取的解码地址。

公开(公告)号：US08788512B2

公开(公告)日：2014-07-22

申请号：US13479132

申请日：2012-05-23

申请人： Sameh W. Asaad ,  Roger Moussalli ,  Bharat Sukhwani

发明人： Sameh W. Asaad ,  Roger Moussalli ,  Bharat Sukhwani

IPC分类号： G06F17/30

CPC分类号： G06F17/30519 ,  G06F17/30516

摘要： Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.

摘要翻译： 提供了生成数据馈送特定解析器电路。 接收与数据馈送特定分析器电路要处理的特定数据馈送相关联的馈送数据的字节数的输入。 描述描述特定数据馈送的数据格式的馈送格式规范文件被解析以生成馈送格式规范文件的内部数据结构。 基于生成的馈送格式指定文件的内部数据结构，确定数据馈送特定解析器电路中用于处理与特定数据相关联的馈送数据的字节数的最小数量的并行流水线级。 然后，生成具有确定数量的并行流水线级的数据馈送特定分析器电路的描述。