公开(公告)号：US11837299B2

公开(公告)日：2023-12-05

申请号：US17716122

申请日：2022-04-08

申请人： Chen-Feng Chang

发明人： Chen-Feng Chang ,  Tien-Sheng Chao

IPC分类号： G11C16/04 ,  G11C17/12 ,  G11C11/56 ,  H10B20/20 ,  H10B43/00

CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

公开(公告)号：US20220343986A1

公开(公告)日：2022-10-27

申请号：US17722534

申请日：2022-04-18

申请人： Chen-Feng CHANG

发明人： Chen-Feng CHANG ,  Tien-Sheng CHAO

IPC分类号： G11C17/12 ,  H01L27/11563 ,  H01L27/112 ,  G11C11/56 ,  G11C16/04

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The present invention breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an ith state, and 1

公开(公告)号：US20120216167A1

公开(公告)日：2012-08-23

申请号：US13504374

申请日：2010-10-27

申请人： Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

发明人： Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/525 ,  H01L24/02 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311

摘要： Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

摘要翻译： 这里公开了用于倒装芯片封装的粗化方法和装置。 倒装芯片包括几个外部焊盘和几个内部焊盘。 路由方法包括：基于外部焊盘的布置顺序设置外部序列; 基于内垫和外垫之间的连接关系设置几个内序列; 计算每个内部序列和外部序列的最长公共子序列，将内部焊盘和对应于最长公共子序列的外部焊盘之间的连接关系定义为直接连接，并且限定内部焊盘和外部焊盘之间的连接关系， 不符合迂回连线最长的共同后果; 基于内部焊盘和外部焊盘之间的连接关系建立倒装芯片的布线方案。

公开(公告)号：US20220328115A1

公开(公告)日：2022-10-13

申请号：US17716122

申请日：2022-04-08

申请人： Chen-Feng CHANG

发明人： Chen-Feng CHANG ,  Tien-Sheng CHAO

IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C11/56 ,  H01L27/112 ,  H01L27/11563

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode, a first oxide located between the first electrode and the conductive gate, and a second oxide located between the second electrode and the conductive gate. The present invention creates an initial state wherein the transistor structure is not conducting, an intermediate state wherein the first oxide is punched through by the first voltage, and a fully opened state wherein both the first oxide and the second oxide are punched through. The aforementioned states allow storage of multiple bits on the read only memory.

公开(公告)号：US12080363B2

公开(公告)日：2024-09-03

申请号：US17722534

申请日：2022-04-18

申请人： Chen-Feng Chang

发明人： Chen-Feng Chang ,  Tien-Sheng Chao

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C17/12 ,  H10B20/20 ,  H10B43/00 ,  H01L29/06 ,  H01L29/423

CPC分类号： G11C17/12 ,  G11C11/5671 ,  G11C16/0466 ,  H10B20/20 ,  H10B43/00 ,  H01L29/0673 ,  H01L29/42392

摘要： An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The operation method breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an ith state, and 1≤ i≤ M. The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.

公开(公告)号：US08578317B2

公开(公告)日：2013-11-05

申请号：US13504374

申请日：2010-10-27

申请人： Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

发明人： Chen-Feng Chang ,  Chin-Fang Shen ,  Hsien-Shih Chiu ,  I-Jye Lin ,  Tien-Chang Hsu ,  Yao-Wen Chang ,  Chun-Wei Lin ,  Po-Wei Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/525 ,  H01L24/02 ,  H01L24/14 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311

摘要： Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

摘要翻译： 这里公开了用于倒装芯片封装的粗化方法和装置。 倒装芯片包括几个外部焊盘和几个内部焊盘。 路由方法包括：基于外部焊盘的布置顺序设置外部序列; 基于内垫和外垫之间的连接关系设置几个内序列; 计算每个内部序列和外部序列的最长公共子序列，将内部焊盘和对应于最长公共子序列的外部焊盘之间的连接关系定义为直接连接，并且限定内部焊盘和外部焊盘之间的连接关系， 不符合迂回连线最长的共同后果; 基于内部焊盘和外部焊盘之间的连接关系建立倒装芯片的布线方案。