公开(公告)号：US20120263002A1

公开(公告)日：2012-10-18

申请号：US13085942

申请日：2011-04-13

申请人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

发明人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

IPC分类号： G11C29/04

CPC分类号： G11C29/025 ,  G11C2029/1204

摘要： A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

摘要翻译： 检测存储器阵列上的制造缺陷的方法可以包括利用测试电路来将存储器阵列的位线上的所选择的电压提供为漏极偏置，其中存储器阵列被配置为使用第一电压作为读取的漏极偏置 并且选择的电压高于第一电压，并且响应于提供所选择的电压作为漏极偏置来确定指示存储器阵列的位线和另一个部件之间的制造缺陷的泄漏电流是否存在。 还提供了相应的测试装置。

公开(公告)号：US08498168B2

公开(公告)日：2013-07-30

申请号：US13085942

申请日：2011-04-13

申请人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

发明人： Yin Chin Huang ,  Chu Pang Huang ,  Yi Fang Chang ,  Cheng Chi Liu ,  Chang Chan Yang ,  Min Kuang Lee

IPC分类号： G11C7/00

CPC分类号： G11C29/025 ,  G11C2029/1204

摘要： A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.

摘要翻译： 检测存储器阵列上的制造缺陷的方法可以包括利用测试电路来将存储器阵列的位线上的所选择的电压提供为漏极偏置，其中存储器阵列被配置为使用第一电压作为读取的漏极偏置 并且选择的电压高于第一电压，并且响应于提供所选择的电压作为漏极偏置来确定指示存储器阵列的位线和另一个部件之间的制造缺陷的泄漏电流是否存在。 还提供了相应的测试装置。

公开(公告)号：US20120127797A1

公开(公告)日：2012-05-24

申请号：US12953213

申请日：2010-11-23

申请人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

发明人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

IPC分类号： G11C29/44 ,  G11C16/26 ,  G11C16/04

CPC分类号： G11C29/50016 ,  G11C11/401

摘要： A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

摘要翻译： 用于测试半导体存储器件的系统和方法包括输入到存储器单元控制栅极的可变电压。 可以将控制栅极的电压从用于正常存储器单元操作（诸如读取操作）的电压电平变化到可用于检测存储器件中的缺陷的电压电平。 在测试期间，施加到控制栅极的电压电平低于施加到存储器单元的诸如漏极端子的第二端子的电压电平。 在一些实施例中，对于缺陷的测试可以包括将负电压施加到控制栅极，同时将正电压施加到漏极端子，这可以揭示栅极 - 漏极泄漏缺陷的存在。

公开(公告)号：US08605525B2

公开(公告)日：2013-12-10

申请号：US12953213

申请日：2010-11-23

申请人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

发明人： Yin Chin Huang ,  Chu Pang Huang ,  Cheng Chi Liu ,  Min Kuang Li ,  Chang Chan Yang ,  Yi Fang Chang

IPC分类号： G11C7/00

CPC分类号： G11C29/50016 ,  G11C11/401

摘要： A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect.

摘要翻译： 用于测试半导体存储器件的系统和方法包括输入到存储器单元控制栅极的可变电压。 可以将控制栅极的电压从用于正常存储器单元操作（诸如读取操作）的电压电平变化到可用于检测存储器件中的缺陷的电压电平。 在测试期间，施加到控制栅极的电压电平低于施加到存储器单元的诸如漏极端子的第二端子的电压电平。 在一些实施例中，对于缺陷的测试可以包括将负电压施加到控制栅极，同时将正电压施加到漏极端子，这可以揭示栅极 - 漏极泄漏缺陷的存在。

公开(公告)号：US08504883B2

公开(公告)日：2013-08-06

申请号：US12868263

申请日：2010-08-25

申请人： Yin-Chin Huang ,  Chu Pang Huang

发明人： Yin-Chin Huang ,  Chu Pang Huang

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A method of testing a semiconductor memory device includes reading previously written test data from the semiconductor memory device simultaneously through at least two data I/O connections, e.g., pins or pads, of the semiconductor memory device. The signals from the two data I/O connections are combined to produce a compound output signal. The compound output signal is received by a single I/O channel of a tester. The tester compares the compound output signal to a predetermined voltage level, and determines whether the semiconductor memory device is operating properly based on the comparison of the compound output signal to the predetermined voltage level.

摘要翻译： 测试半导体存储器件的方法包括通过半导体存储器件的至少两个数据I / O连接（例如引脚或焊盘）同时从半导体存储器件读取先前写入的测试数据。 来自两个数据I / O连接的信号被组合以产生复合输出信号。 复合输出信号由测试仪的单个I / O通道接收。 测试仪将复合输出信号与预定电压电平进行比较，并根据复合输出信号与预定电压电平的比较，确定半导体存储器件是否正常工作。

公开(公告)号：US20120054565A1

公开(公告)日：2012-03-01

申请号：US12868263

申请日：2010-08-25

申请人： Yin-Chin Huang ,  Chu Pang Huang

发明人： Yin-Chin Huang ,  Chu Pang Huang

IPC分类号： G11C29/10 ,  G06F11/263

CPC分类号： G11C29/26 ,  G11C2029/2602 ,  G11C2029/5602

摘要： A method of testing a semiconductor memory device includes reading previously written test data from the semiconductor memory device simultaneously through at least two data I/O connections, e.g., pins or pads, of the semiconductor memory device. The signals from the two data I/O connections are combined to produce a compound output signal. The compound output signal is received by a single I/O channel of a tester. The tester compares the compound output signal to a predetermined voltage level, and determines whether the semiconductor memory device is operating properly based on the comparison of the compound output signal to the predetermined voltage level

摘要翻译： 测试半导体存储器件的方法包括通过半导体存储器件的至少两个数据I / O连接（例如引脚或焊盘）同时从半导体存储器件读取先前写入的测试数据。 来自两个数据I / O连接的信号被组合以产生复合输出信号。 复合输出信号由测试仪的单个I / O通道接收。 测试器将复合输出信号与预定电压电平进行比较，并且基于复合输出信号与预定电压电平的比较来确定半导体存储器件是否正常工作

公开(公告)号：US08351286B2

公开(公告)日：2013-01-08

申请号：US12842605

申请日：2010-07-23

申请人： Yin Chin Huang ,  Chu Pang Huang

发明人： Yin Chin Huang ,  Chu Pang Huang

IPC分类号： G11C7/00

CPC分类号： G11C29/025 ,  G11C29/10

摘要： A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell at an intersection of the program conductive line and a conductive line extending in a second direction to a selected high value, and determining whether a cell initially at a low value and associated with a conductive line extending in the first direction and adjacent to the program conductive line is disturbed.

摘要翻译： 筛选存储器阵列上的制造缺陷的方法可以包括沿沿着第一方向延伸的导电线编程物理反向数据的背景图案。 编程可以包括提供具有高值的程序导线。 该方法还可以包括在存储器单元的编程导线和在第二方向上延伸到选定的高值的导线之间的交点处编程存储器单元，以及确定初始处于低值并且与导线延伸相关联的单元 第一个方向和相邻的程序导线受到干扰。

公开(公告)号：US20120020164A1

公开(公告)日：2012-01-26

申请号：US12842605

申请日：2010-07-23

申请人： Yin Chin Huang ,  Chu Pang Huang

发明人： Yin Chin Huang ,  Chu Pang Huang

IPC分类号： G11C16/04

CPC分类号： G11C29/025 ,  G11C29/10

摘要： A method of screening manufacturing defects at a memory array may include programming a background pattern of physically inverse data along conductive lines extending in a first direction. The programming may include providing a program conductive line with a high value. The method may further include programming a memory cell at an intersection of the program conductive line and a conductive line extending in a second direction to a selected high value, and determining whether a cell initially at a low value and associated with a conductive line extending in the first direction and adjacent to the program conductive line is disturbed.

摘要翻译： 筛选存储器阵列上的制造缺陷的方法可以包括沿沿着第一方向延伸的导电线编程物理反向数据的背景图案。 编程可以包括提供具有高值的程序导线。 该方法还可以包括在存储器单元的编程导线和在第二方向上延伸到选定的高值的导线之间的交点处编程存储器单元，以及确定初始处于低值并且与导线延伸相关联的单元 第一个方向和相邻的程序导线受到干扰。