公开(公告)号：US20090066406A1

公开(公告)日：2009-03-12

申请号：US11898384

申请日：2007-09-12

Applicant: Hsin Chang Lin ,  Cheng Ying Wu

Inventor： Hsin Chang Lin ,  Cheng Ying Wu

IPC: G05F3/02

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

Abstract translation: 提出一种电荷泵装置及其操作方法。 电荷泵装置由多级电荷转移单元和串联在一起的输出单元组成。 电荷转移单元的每一级包括用于输入的第一节点，用于输出的第二节点，第一电路和第一电容器。 第一节点或第二节点以为第一电路提供的偏置而偏置。 因此，奇数级的第一电容器和偶数级的电荷转移单元可分别接收相互相反的两个时钟信号，用于互补开关操作。 与输出单元的切换配合，可以产生具有高负电平的输出电压。

公开(公告)号：US20080035973A1

公开(公告)日：2008-02-14

申请号：US11463600

申请日：2006-08-10

Applicant: Hsin Chang Lin ,  Wen Chien Huang ,  Hao Cheng Chang ,  Cheng Ying Wu ,  Ming Tsang Yang

Inventor： Hsin Chang Lin ,  Wen Chien Huang ,  Hao Cheng Chang ,  Cheng Ying Wu ,  Ming Tsang Yang

IPC: H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11558

Abstract: The present invention discloses a low-noise single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the electrically-conductive gate of the transistor and the electrically-conductive gate of the capacitor structure are interconnected to form a single floating gate of a memory cell; an ion-doped buried layer is formed between the dielectric layer of the capacitor structure and the semiconductor substrate to reduce the external interference on the capacitor structure and control the initial threshold voltage; a reverse bias may be used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of the low-noise single-gate non-volatile memory having an isolation well, positive and negative voltages may be applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer, and thereby, the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract translation: 本发明公开了一种低噪声单栅极非易失性存储器及其操作方法，其中晶体管和电容器结构嵌入在半导体衬底中; 晶体管的导电栅极和电容器结构的导电栅极互连以形成存储单元的单个浮置栅极; 在电容器结构的电介质层和半导体衬底之间形成离子掺杂掩埋层，以减小对电容器结构的外部干扰并控制初始阈值电压; 可以使用反向偏置来实现单浮栅存储单元的读，写和擦除操作; 在具有隔离阱的低噪声单栅极非易失性存储器的操作中，可以将正电压和负电压施加到漏极，栅极和硅衬底/隔离阱以产生反转层，从而 ，可以降低绝对电压，升压电路的面积和电流消耗。

公开(公告)号：US06125097A

公开(公告)日：2000-09-26

申请号：US186423

申请日：1998-11-05

Applicant: Cheng-Ying Wu

Inventor： Cheng-Ying Wu

IPC: G11B33/08

CPC classification number: G11B33/08

Abstract: A shock absorbing device adapted to be incorporated in a reading mechanism of a CD-ROM having a driving motor of a substantial weight arranged at a first end side of the reading mechanism, includes a base frame defining therein an interior space for receiving and holding the reading mechanism therein. A plurality of shock absorbing elements, made of a resilient material, are arranged between the reading mechanism and support members that are fixed inside the interior space of the base frame for absorbing vibration/shock caused by the operation of the CD-ROM. At least one counterweight plate is attached to the reading mechanism at a second end side thereof to be opposite to the driving motor in order to balance the weight of the motor.

Abstract translation: 一种适于结合在具有布置在读取机构的第一端侧的具有实质重量的驱动电机的CD-ROM的读取机构中的减震装置，包括：底座，其限定内部空间，用于接收和保持 阅读机制。 多个由弹性材料制成的减震元件布置在读取机构和固定在基座的内部空间内的支撑构件之间，用于吸收由CD-ROM的操作引起的振动/冲击。 至少一个配重板在其第二端侧附接到读取机构以与驱动电机相对，以平衡电动机的重量。

公开(公告)号：US07423903B2

公开(公告)日：2008-09-09

申请号：US11403858

申请日：2006-04-14

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: G11C14/00

CPC classification number: H01L27/115

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract translation: 一种单栅极非易失性存储器及其操作方法，其中晶体管和电容器结构嵌入在半导体衬底中; 所述晶体管包括：第一导电栅极，第一介电层和多个离子掺杂区域; 电容器结构包括：第二导电栅极，第二介电层和第二掺杂区域; 第一导电栅极和第二导电栅极互连以形成存储单元的单个浮置栅极; 使用反向偏置来实现单浮栅存储单元的读，写和擦除操作; 在具有隔离阱的单栅极非易失性存储器的操作中，正和负电压施加到漏极，栅极和硅衬底/隔离阱以产生反型层，使得绝对电压 升压电路的面积，可以减少电流消耗。

公开(公告)号：US20070241392A1

公开(公告)日：2007-10-18

申请号：US11403862

申请日：2006-04-14

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825

Abstract: A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.

Abstract translation: 提出了一种非易失性存储器结构及其操作方法。 非易失性存储器结构使用单个浮置栅极结构和包括掺杂有不同类型杂质的一对区域的电容器结构，以增加电容并缩小面积。 当对该存储器结构执行编程操作时，将电压施加到源极，或者向晶体管的衬底施加反偏压，以大大降低单栅极EEPROM器件的电流需求。 当执行擦除操作时，漏极电压升高，并且向栅极添加小电压以增加F-N隧穿电流，从而实现快速擦除的效果。

公开(公告)号：US07508253B1

公开(公告)日：2009-03-24

申请号：US11898384

申请日：2007-09-12

Applicant: Cheng Ying Wu ,  Hsin Chang Lin

Inventor： Cheng Ying Wu ,  Hsin Chang Lin

IPC: G06G7/26 ,  G06G7/12

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

Abstract translation: 提出一种电荷泵装置及其操作方法。 电荷泵装置由多级电荷转移单元和串联在一起的输出单元组成。 电荷转移单元的每一级包括用于输入的第一节点，用于输出的第二节点，第一电路和第一电容器。 第一节点或第二节点以为第一电路提供的偏置而偏置。 因此，奇数级的第一电容器和偶数级的电荷转移单元可分别接收相互相反的两个时钟信号，用于互补开关操作。 与输出单元的切换配合，可以产生具有高负电平的输出电压。

公开(公告)号：US20080173915A1

公开(公告)日：2008-07-24

申请号：US12076963

申请日：2008-03-26

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: H01L29/94

CPC classification number: H01L27/115

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

公开(公告)号：US20070241383A1

公开(公告)日：2007-10-18

申请号：US11403858

申请日：2006-04-14

Applicant: Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

Inventor： Hsin-Chang Lin ,  Wen-Chien Huang ,  Ming-Tsang Yang ,  Hao-Cheng Chang ,  Cheng-Ying Wu

IPC: H01L29/94

CPC classification number: H01L27/115

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract translation: 一种单栅极非易失性存储器及其操作方法，其中晶体管和电容器结构嵌入在半导体衬底中; 所述晶体管包括：第一导电栅极，第一介电层和多个离子掺杂区域; 电容器结构包括：第二导电栅极，第二介电层和第二掺杂区域; 第一导电栅极和第二导电栅极互连以形成存储单元的单个浮置栅极; 使用反向偏置来实现单浮栅存储单元的读，写和擦除操作; 在具有隔离阱的单栅极非易失性存储器的操作中，正和负电压施加到漏极，栅极和硅衬底/隔离阱以产生反型层，使得绝对电压 升压电路的面积，可以减少电流消耗。