公开(公告)号：US20090066406A1

公开(公告)日：2009-03-12

申请号：US11898384

申请日：2007-09-12

Applicant: Hsin Chang Lin ,  Cheng Ying Wu

Inventor： Hsin Chang Lin ,  Cheng Ying Wu

IPC: G05F3/02

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

Abstract translation: 提出一种电荷泵装置及其操作方法。 电荷泵装置由多级电荷转移单元和串联在一起的输出单元组成。 电荷转移单元的每一级包括用于输入的第一节点，用于输出的第二节点，第一电路和第一电容器。 第一节点或第二节点以为第一电路提供的偏置而偏置。 因此，奇数级的第一电容器和偶数级的电荷转移单元可分别接收相互相反的两个时钟信号，用于互补开关操作。 与输出单元的切换配合，可以产生具有高负电平的输出电压。

公开(公告)号：US20080035973A1

公开(公告)日：2008-02-14

申请号：US11463600

申请日：2006-08-10

Applicant: Hsin Chang Lin ,  Wen Chien Huang ,  Hao Cheng Chang ,  Cheng Ying Wu ,  Ming Tsang Yang

Inventor： Hsin Chang Lin ,  Wen Chien Huang ,  Hao Cheng Chang ,  Cheng Ying Wu ,  Ming Tsang Yang

IPC: H01L29/94

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11558

Abstract: The present invention discloses a low-noise single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the electrically-conductive gate of the transistor and the electrically-conductive gate of the capacitor structure are interconnected to form a single floating gate of a memory cell; an ion-doped buried layer is formed between the dielectric layer of the capacitor structure and the semiconductor substrate to reduce the external interference on the capacitor structure and control the initial threshold voltage; a reverse bias may be used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of the low-noise single-gate non-volatile memory having an isolation well, positive and negative voltages may be applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer, and thereby, the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract translation: 本发明公开了一种低噪声单栅极非易失性存储器及其操作方法，其中晶体管和电容器结构嵌入在半导体衬底中; 晶体管的导电栅极和电容器结构的导电栅极互连以形成存储单元的单个浮置栅极; 在电容器结构的电介质层和半导体衬底之间形成离子掺杂掩埋层，以减小对电容器结构的外部干扰并控制初始阈值电压; 可以使用反向偏置来实现单浮栅存储单元的读，写和擦除操作; 在具有隔离阱的低噪声单栅极非易失性存储器的操作中，可以将正电压和负电压施加到漏极，栅极和硅衬底/隔离阱以产生反转层，从而 ，可以降低绝对电压，升压电路的面积和电流消耗。

公开(公告)号：US07508253B1

公开(公告)日：2009-03-24

申请号：US11898384

申请日：2007-09-12

Applicant: Cheng Ying Wu ,  Hsin Chang Lin

Inventor： Cheng Ying Wu ,  Hsin Chang Lin

IPC: G06G7/26 ,  G06G7/12

CPC classification number: H02M3/073 ,  H02M2003/078

Abstract: A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

Abstract translation: 提出一种电荷泵装置及其操作方法。 电荷泵装置由多级电荷转移单元和串联在一起的输出单元组成。 电荷转移单元的每一级包括用于输入的第一节点，用于输出的第二节点，第一电路和第一电容器。 第一节点或第二节点以为第一电路提供的偏置而偏置。 因此，奇数级的第一电容器和偶数级的电荷转移单元可分别接收相互相反的两个时钟信号，用于互补开关操作。 与输出单元的切换配合，可以产生具有高负电平的输出电压。

公开(公告)号：US08218369B2

公开(公告)日：2012-07-10

申请号：US12692868

申请日：2010-01-25

Applicant: Hsin Chang Lin ,  Wen-Chien Huang

Inventor： Hsin Chang Lin ,  Wen-Chien Huang

IPC: G11C16/02

CPC classification number: H01L29/7885 ,  G11C16/0416 ,  G11C16/14 ,  G11C16/3418

Abstract: A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.

Abstract translation: 非易失性存储器低电压和高速擦除方法，通过在半导体衬底或隔离阱中设置具有控制栅极和浮置栅极的堆叠栅极结构来实现非易失性存储器，使得足够的热孔为 通过漏极反向偏压进行低电压和高速擦除操作而产生，并改变栅极电压。 此外，通过在漏极，栅极和半导体衬底或阱区域上施加正电压和负电压，产生足够的热孔，从而降低绝对电压以实现降低擦除存储器电压的目的。

公开(公告)号：US11130102B2

公开(公告)日：2021-09-28

申请号：US16233578

申请日：2018-12-27

Applicant: Cheng Chi Tai ,  Hsin Chang Lin ,  Chun Hao Lu

Inventor： Cheng Chi Tai ,  Hsin Chang Lin ,  Chia Ming Houng

IPC: B01F9/00 ,  H02J50/10 ,  B01F15/00 ,  B01F9/10

Abstract: A mixer for mixing and degassing fluids includes a revolution device having a revolution base to be driven for rotation; a first spin device connected to the revolution base of the revolution device; a first barrel connected to the first spin device to be spun by the first spin device; an transmitting coil electrically connected to a power source to generate a time-vary magnetic field; and a receiving coil connected to the revolution base of the revolution device and electrically connected to the first spin device, wherein the receiving coil rotates with the revolution base. The receiving coil receives the power from the time-vary magnetic field of the transmitting coil and produces an electromotive force to be supplied to the first spin device.

公开(公告)号：US08305808B2

公开(公告)日：2012-11-06

申请号：US12854989

申请日：2010-08-12

Applicant: Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

Inventor： Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

IPC: G11C11/34

CPC classification number: G11C16/0416 ,  G11C16/0483 ,  G11C16/14 ,  H01L29/7881

Abstract: A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.

Abstract translation: 公开了一种低电压EEPROM阵列，其具有多个并行位线，并行字线和并行公共源极线。 位线包括第一位线。 字线包括第一字线和第二字线。 公共源极线包括第一公共源极线和第二公共源极线。 低电压EEPROM阵列还具有多个子存储器阵列。 每个子存储器阵列包括第一存储单元和第二存储单元。 第一存储单元与第一位线，第一公共源极线和第一字线连接。 第二存储单元与第一位线，第二公共源极线和第二字线连接。 第一和第二存储单元是对称的并且布置在第一和第二公共源极线之间。

公开(公告)号：US20090185429A1

公开(公告)日：2009-07-23

申请号：US12010121

申请日：2008-01-22

Applicant: Hsin Chang Lin ,  Wen Chien Huang ,  Ming Tsang Yang

Inventor： Hsin Chang Lin ,  Wen Chien Huang ,  Ming Tsang Yang

IPC: G11C16/06 ,  H01L29/788

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/788

Abstract: A non-volatile memory with single floating gate and the method for operating the same are proposed. The non-volatile memory is formed by embedding a FET structure in a semiconductor substrate. The FET comprises a single floating gate, a dielectric, and two ion-doped regions in the semiconductor at two sides of the dielectric. The memory cell of the proposed nonvolatile memory with single floating gate can perform many times of operations such as write, erase and read by means of a reverse bias.

Abstract translation: 提出了具有单个浮动栅极的非易失性存储器及其操作方法。 非易失性存储器通过在半导体衬底中嵌入FET结构而形成。 FET包括在电介质的两侧的半导体中的单个浮置栅极，电介质层和两个离子掺杂区域。 所提出的具有单个浮动栅极的非易失性存储器的存储单元可以通过反向偏置执行许多次操作，例如写入，擦除和读取。

公开(公告)号：US08300469B2

公开(公告)日：2012-10-30

申请号：US12854407

申请日：2010-08-11

Applicant: Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

Inventor： Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

IPC: G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0441

Abstract: A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Abstract translation: 一种节省成本的EEPROM阵列，具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线包含第一组位线; 字线包括第一和第二字线; 并且公共源极线包括第一公共源极线。 并且，提供多个子存储器阵列。 每个子存储器阵列包括彼此相对设置并位于第一公共源极线的两个不同侧上的第​​一和第二存储单元; 第一存储单元连接到第一组位线，第一公共源极线和第一字线，并且第二存储单元连接到第一组位线，第一公共源极线和第二字线 。

公开(公告)号：US08300461B2

公开(公告)日：2012-10-30

申请号：US12862082

申请日：2010-08-24

Applicant: Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

Inventor： Hsin Chang Lin ,  Chia-Hao Tai ,  Yang-Sen Yen ,  Ming-Tsang Yang ,  Ya-Ting Fan

IPC: G11C11/34

CPC classification number: G11C16/0416

Abstract: An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.

Abstract translation: 一种保存电可擦除可编程只读存储器（EEPROM）阵列的区域，其具有：多个并行位线，多个并行字线和多个并行公共源极线。 位线分为多个位线组，包含第一组位线和第二组位线; 字线包括第一字线; 并且公共源极线包括第一公共源极线。 另外，提供了多个子存储器阵列。 每个子存储器阵列包含第一，第二，第三和第四存储器单元。 其中，第一和第二存储单元是对称排列的，第三和第四存储单元是对称排列的; 第一和第二存储单元以及第三和第四存储单元也以第一公共源极线为对称轴对称地布置。

公开(公告)号：US07099192B2

公开(公告)日：2006-08-29

申请号：US10861392

申请日：2004-06-07

Applicant: Lee Zhung Wang ,  Daniel Huang ,  Hsin Chang Lin ,  Roget Chang

Inventor： Lee Zhung Wang ,  Daniel Huang ,  Hsin Chang Lin ,  Roget Chang

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C16/3477 ,  G11C2216/10

Abstract: A nonvolatile memory and a method of operating the same are proposed. The nonvolatile memory has single-gate memory cells, wherein a structure of a transistor and a capacitor is embedded in a semiconductor substrate. The transistor comprises a first conducting gate stacked on the surface of a dielectric with doped regions formed at two sides thereof as a source and a drain. The capacitor comprises a doped region, a dielectric stacked thereon, and a second conducting gate. The conducting gates of the capacitor and the transistor are electrically connected together to form a single floating gate of the memory cell. The semiconductor substrate is p-type or n-type. Besides, a back-bias program write-in and related erase and readout operation ways are proposed for the single-gate memory cells.

Abstract translation: 提出了一种非易失性存储器及其操作方法。 非易失性存储器具有单栅极存储单元，其中晶体管和电容器的结构嵌入在半导体衬底中。 晶体管包括堆叠在电介质的表面上的第一导电栅极，其掺杂区域形成在其两侧作为源极和漏极。 电容器包括掺杂区域，堆叠在其上的电介质和第二导电栅极。 电容器和晶体管的导通栅极电连接在一起以形成存储单元的单个浮置栅极。 半导体衬底是p型或n型。 此外，针对单栅极存储器单元提出了背偏置程序写入和相关的擦除和读出操作方式。