Semiconductor device structure for reducing hot carrier effect of MOS transistor
    1.
    发明授权
    Semiconductor device structure for reducing hot carrier effect of MOS transistor 有权
    用于降低MOS晶体管热载流子效应的半导体器件结构

    公开(公告)号:US07602003B2

    公开(公告)日:2009-10-13

    申请号:US10908071

    申请日:2005-04-27

    IPC分类号: H01L29/94 H01L29/78

    摘要: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.

    摘要翻译: 描述了包括MOS晶体管,折射率为约2.00-2.30的富硅氮化硅层和介电层的半导体器件结构。 富硅氮化硅层设置在MOS晶体管和电介质层之间,并且覆盖MOS晶体管的源/漏区,间隔物和栅极导体。

    Salicide process
    2.
    发明授权
    Salicide process 有权
    自杀过程

    公开(公告)号:US07238611B2

    公开(公告)日:2007-07-03

    申请号:US10907710

    申请日:2005-04-13

    IPC分类号: H01L21/4763

    CPC分类号: H01L29/665 H01L21/28518

    摘要: A salicide process is provided. A metal layer selected from a group consisting of titanium, cobalt, platinum, palladium and an alloy thereof is formed over a silicon layer. A first thermal process is performed. Next, a second thermal process is performed, wherein the second thermal process includes a first step performed at 600˜700 degrees centigrade for 10˜60 seconds and a second step performed at 750˜850 degrees centigrade for 10˜60 seconds. If the metal layer is selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.

    摘要翻译: 提供自杀过程。 在硅层上形成由钛,钴,铂,钯及其合金组成的组中选择的金属层。 执行第一热处理。 接下来,进行第二热处理,其中第二热处理包括在600〜700摄氏度下进行10〜60秒的第一步骤,在750〜850摄氏度下进行10〜60秒的第二步骤。 如果在硅层上形成由镍组成的组中的金属层和合金,则在300〜400℃进行10〜60秒的第二热处理的第1工序, 第二次热处理在450〜550摄氏度进行10〜60秒。

    Planarization process
    3.
    发明授权
    Planarization process 失效
    平面化过程

    公开(公告)号:US06211097B1

    公开(公告)日:2001-04-03

    申请号:US09223398

    申请日:1998-12-30

    IPC分类号: H01L2131

    摘要: This invention provides a planarization method that solves the microscratch problem caused by chemical-mechanical polishing. This method comprises the following steps: providing a substrate with semiconductor devices, forming a SRO oxide on the substrate, forming a SOG layer on the SRO layer, performing a curing process, performing an implantation process during the curing process, forming an oxide layer on the SRO oxide, and planarizing the oxide layer by CMP. Another SOG layer is formed on the planarized oxide layer, a curing process is performed on the second SOG layer, and a cap oxide layer is formed on the second SOG layer to adjust the thickness of the dielectric layer. This invention can solve conventional problems such as microscratching and metal bridges.

    摘要翻译: 本发明提供了解决化学机械抛光引起的微观问题的平面化方法。 该方法包括以下步骤:向衬底提供半导体器件,在衬底上形成SRO氧化物,在SRO层上形成SOG层,进行固化过程,在固化过程中进行注入工艺,形成氧化层 SRO氧化物,并通过CMP平坦化氧化物层。 在平坦化氧化物层上形成另一SOG层,对第二SOG层进行固化处理,在第二SOG层上形成帽氧化层,调整电介质层的厚度。 本发明可以解决诸如显微划线和金属桥的常规问题。

    Method of forming a contact via
    4.
    发明授权
    Method of forming a contact via 失效
    形成接触通孔的方法

    公开(公告)号:US5960321A

    公开(公告)日:1999-09-28

    申请号:US879199

    申请日:1997-06-19

    CPC分类号: H01L21/76801

    摘要: A method of forming a contact via includes forming a wiring, a first insulator layer, and a spin-on glass layer, respectively, over a semiconductor substrate. Fluorine ions are implanted into the spin-on glass layer. A second insulator layer is formed over the spin-on glass layer. The wiring is exposed by patterning the second insulator layer, the spin-on glass layer, and the first insulator layer, respectively.

    摘要翻译: 形成接触通孔的方法包括分别在半导体衬底上形成布线,第一绝缘体层和旋涂玻璃层。 将氟离子注入到旋涂玻璃层中。 在旋涂玻璃层上形成第二绝缘体层。 通过图案化第二绝缘体层,旋涂玻璃层和第一绝缘体层来分别布线。

    Method for reducing hot carrier effect of MOS transistor
    5.
    发明授权
    Method for reducing hot carrier effect of MOS transistor 有权
    降低MOS晶体管热载流子效应的方法

    公开(公告)号:US07579250B2

    公开(公告)日:2009-08-25

    申请号:US11830783

    申请日:2007-07-30

    IPC分类号: H01L21/336 H01L21/8238

    摘要: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.

    摘要翻译: 描述了包括MOS晶体管,折射率为约2.00-2.30的富硅氮化硅层和介电层的半导体器件结构。 富硅氮化硅层设置在MOS晶体管和电介质层之间,并且覆盖MOS晶体管的源/漏区,间隔物和栅极导体。

    SALICIDE PROCESS
    6.
    发明申请
    SALICIDE PROCESS 有权
    杀菌工艺

    公开(公告)号:US20070048986A1

    公开(公告)日:2007-03-01

    申请号:US11553477

    申请日:2006-10-27

    IPC分类号: H01L21/336

    CPC分类号: H01L29/665 H01L21/28518

    摘要: A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.

    摘要翻译: 提供自杀过程。 在硅层上形成由镍及其合金构成的组中选择的金属层,第二热处理的第一工序在300〜400℃进行10〜60秒,第二工序 工艺在450〜550摄氏度下进行10〜60秒。

    METHOD FOR REDUCING HOT CARRIER EFFECT OF MOS TRANSISTOR
    8.
    发明申请
    METHOD FOR REDUCING HOT CARRIER EFFECT OF MOS TRANSISTOR 有权
    减少MOS晶体管的热载流子效应的方法

    公开(公告)号:US20080038937A1

    公开(公告)日:2008-02-14

    申请号:US11830783

    申请日:2007-07-30

    IPC分类号: H01L21/31

    摘要: A semiconductor device structure is described, including a MOS transistor, a silicon-rich silicon nitride layer having a refractive index of about 2.00-2.30, and a dielectric layer. The silicon-rich silicon nitride layer is disposed between the MOS transistor and the dielectric layer, and covers the source/drain region, the spacer and the gate conductor of the MOS transistor.

    摘要翻译: 描述了包括MOS晶体管,折射率为约2.00-2.30的富硅氮化硅层和介电层的半导体器件结构。 富硅氮化硅层设置在MOS晶体管和电介质层之间,并且覆盖MOS晶体管的源/漏区,间隔物和栅极导体。

    Salicide process
    9.
    发明授权
    Salicide process 有权
    自杀过程

    公开(公告)号:US07285491B2

    公开(公告)日:2007-10-23

    申请号:US11553477

    申请日:2006-10-27

    IPC分类号: H01L21/44

    CPC分类号: H01L29/665 H01L21/28518

    摘要: A salicide process is provided. A metal layer selected from a group consisting of nickel and an alloy thereof is formed on a silicon layer, the first step of the second thermal process is performed at 300˜400 degrees centigrade for 10˜60 seconds and the second step of the second thermal process is performed at 450˜550 degrees centigrade for 10˜60 seconds.

    摘要翻译: 提供自杀过程。 在硅层上形成由镍及其合金组成的组中选择的金属层,第二热处理的第一步骤在300〜400摄氏度下进行10〜60秒,第二次热处理 工艺在450〜550摄氏度下进行10〜60秒。

    Method for forming inter-metal dielectrics
    10.
    发明授权
    Method for forming inter-metal dielectrics 失效
    形成金属间电介质的方法

    公开(公告)号:US06265298B1

    公开(公告)日:2001-07-24

    申请号:US09249882

    申请日:1999-02-16

    IPC分类号: H01L2144

    摘要: An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the cured third dielectric layer. A chemical-mechanical polishing process is performed using the cured dielectric layer as a stop layer. A cap layer is formed on the fourth dielectric layer.

    摘要翻译: 提供了一种用于在半导体衬底上形成金属间电介质(IMD)的改进方法,其中在其上形成导电线。 在导电线上形成第一介电层。 通过旋涂玻璃法在第一介电层上形成第二介电层。 执行具有低能量和高剂量的电子束的固化处理以固化第二介电层的上部,使得固化的第三介电层形成在第二介电层上。 在固化的第三电介质层上形成第四电介质层。 使用固化的电介质层作为停止层进行化学机械抛光工艺。 在第四电介质层上形成覆盖层。