公开(公告)号：US20130217221A1

公开(公告)日：2013-08-22

申请号：US13398991

申请日：2012-02-17

申请人： Chris M. PRINDLE ,  Klaus Hempel ,  Andy C. Wei

发明人： Chris M. PRINDLE ,  Klaus Hempel ,  Andy C. Wei

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545

摘要： Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

摘要翻译： 半导体器件形成有最后的高K /金属栅极工艺，完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极，虚拟栅电极具有氮化物盖，在虚拟栅电极的相对侧上形成隔板，在其间形成栅极沟槽，干蚀刻氮化物盖，使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻，并湿法蚀刻伪栅电极的其余部分。

公开(公告)号：US08673759B2

公开(公告)日：2014-03-18

申请号：US13398991

申请日：2012-02-17

申请人： Chris M. Prindle ,  Klaus Hempel ,  Andy C. Wei

发明人： Chris M. Prindle ,  Klaus Hempel ,  Andy C. Wei

IPC分类号： H01L21/28

CPC分类号： H01L21/28114 ,  H01L21/32131 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/66545

摘要： Semiconductor devices are formed with a gate last, high-K/metal gate process with complete removal of the polysilicon dummy gate and with a gap having a low aspect ratio for the metal fill. Embodiments include forming a dummy gate electrode on a substrate, the dummy gate electrode having a nitride cap, forming spacers adjacent opposite sides of the dummy gate electrode forming a gate trench therebetween, dry etching the nitride cap, tapering the gate trench top corners; performing a selective dry etch on a portion of the dummy gate electrode, and wet etching the remainder of the dummy gate electrode.

摘要翻译： 半导体器件形成有最后的高K /金属栅极工艺，完全去除多晶硅虚拟栅极并且具有用于金属填充物的低纵横比的间隙。 实施例包括在基板上形成虚拟栅电极，虚拟栅电极具有氮化物盖，在虚拟栅电极的相对侧上形成隔板，在其间形成栅极沟槽，干蚀刻氮化物盖，使栅极沟槽顶角逐渐变细; 在虚拟栅电极的一部分上进行选择性干蚀刻，并湿法蚀刻伪栅电极的其余部分。