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公开(公告)号：US08181098B2
公开(公告)日：2012-05-15
申请号：US12157512
申请日：2008-06-11
IPC分类号： G06F11/00
CPC分类号： H03M13/4115 , H03M13/09 , H03M13/27 , H03M13/41 , H03M13/6362 , H04L1/0054
摘要： Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
摘要翻译： 维特比解码器中的方法和对应系统包括响应于执行第一维特比算法计算维特比网格中的最大似然（ML）路径。 此后，在第二维特比算法中在ML路径上选择一个或多个合并点，其中合并点各自具有路径度量差异，其是合并点处的ML路径度量与不存在路径度量 在合并点。 基于与ML路径上的节点相关联的相对路径度量差选择合并点。 接下来，维特比网格中的替代路径是基于ML路径计算的，其中替代路径在相应的合并点处被替换。 经过解码的比特序列响应于通过错误检查被输出，其中通过解码的比特序列与一个或多个替代路径中的一个相关联。
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公开(公告)号：US08099657B2
公开(公告)日：2012-01-17
申请号：US12218183
申请日：2008-07-11
IPC分类号： H03M13/03
CPC分类号： H04L1/0054 , H03M13/3738 , H03M13/3746 , H03M13/41 , H04L1/0052
摘要： Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
摘要翻译： 维特比解码器中的方法和对应系统包括选择输入块中的输入符号，其中输入块具有多个输入符号，其中每个输入符号具有布尔值，质量值和相关级，并且其中 基于所选符号的质量值相对于输入块中的其他输入符号的质量值来选择所选择的符号。 此后，补充所选符号的布尔值以产生补码。 替代了所选符号以产生替代输入块。 使用替代输入块执行维特比算法来产生替代解码比特序列，然后使用错误检查来检查错误。 响应于通过错误检查的替代解码比特序列输出替代解码比特序列。
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公开(公告)号：US20090313530A1
公开(公告)日：2009-12-17
申请号：US12157512
申请日：2008-06-11
CPC分类号： H03M13/4115 , H03M13/09 , H03M13/27 , H03M13/41 , H03M13/6362 , H04L1/0054
摘要： Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
摘要翻译： 维特比解码器中的方法和对应系统包括响应于执行第一维特比算法计算维特比网格中的最大似然（ML）路径。 此后，在第二维特比算法中在ML路径上选择一个或多个合并点，其中合并点各自具有路径度量差异，其是合并点处的ML路径度量与不存在路径度量 在合并点。 基于与ML路径上的节点相关联的相对路径度量差选择合并点。 接下来，维特比网格中的替代路径是基于ML路径计算的，其中替代路径在相应的合并点处被替换。 经过解码的比特序列响应于通过错误检查被输出，其中通过解码的比特序列与一个或多个替代路径中的一个相关联。
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公开(公告)号：US20100011279A1
公开(公告)日：2010-01-14
申请号：US12218183
申请日：2008-07-11
CPC分类号： H04L1/0054 , H03M13/3738 , H03M13/3746 , H03M13/41 , H04L1/0052
摘要： Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
摘要翻译： 维特比解码器中的方法和对应系统包括选择输入块中的输入符号，其中输入块具有多个输入符号，其中每个输入符号具有布尔值，质量值和相关级，并且其中 基于所选符号的质量值相对于输入块中的其他输入符号的质量值来选择所选择的符号。 此后，补充所选符号的布尔值以产生补码。 替代了所选符号以产生替代输入块。 使用替代输入块执行维特比算法来产生替代解码比特序列，然后使用错误检查来检查错误。 响应于通过错误检查的替代解码比特序列输出替代解码比特序列。
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公开(公告)号：US08015470B2
公开(公告)日：2011-09-06
申请号：US11779499
申请日：2007-07-18
IPC分类号： G11C29/00
CPC分类号： H04L27/0012 , H04L27/0008
摘要： A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.
摘要翻译： 解码电路包括响应于突发拒绝信息的混合调制存储器访问电路。 混合调制存储器访问电路选择性地访问包含编码比特的有效突发的突发存储器位置。 混合调制存储器访问电路基于突发拒绝信息选择性地避免访问包含被拒绝的编码比特的突发的突发存储器位置。 在一个示例中，当突发拒绝信息指示存储器位置包含有效突发时，混合调制存储器访问电路访问有效突发。 在一个示例中，当突发拒绝信息指示存储器位置包含拒绝的突发时，混合调制存储器访问电路产生零置信度信息。
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6.发明授权Method and mobile station for reporting multi-path signals based on minimum separation 有权基于最小间隔报告多径信号的方法和移动台公开(公告)号：US06873826B2
公开(公告)日：2005-03-29
申请号：US10213805
申请日：2002-08-06
CPC分类号： H04W48/20 , H04B1/7113 , H04B1/7117
摘要： A method (700) and a mobile station (160) for reporting multi-path signals based on minimum separation are described herein. The mobile station (160) may include a list with a first energy/position pair corresponding to the energy parameter and the position parameter associated with a first multi-path signal of a synchronization code. The mobile station (160) may generate a second energy/position pair corresponding to the energy parameter and the position parameter of a second multi-path signal. The mobile station (160) may detect the position parameter of the second energy/position pair being within a minimum separation associated with the position parameter of the first energy/position pair. The mobile station (160) may also detect the energy parameter of the second energy/position pair being greater than the energy parameter of the first energy/position pair. Accordingly, the mobile station (160) may replace the first energy/position pair on the list with the second energy/position pair.
摘要翻译： 这里描述了用于基于最小间隔报告多路径信号的方法（700）和移动站（160）。 移动站（160）可以包括具有对应于能量参数的第一能量/位置对和与同步码的第一多路径信号相关联的位置参数的列表。 移动站（160）可以产生对应于能量参数和第二多路径信号的位置参数的第二能量/位置对。 移动站（160）可以检测第二能量/位置对的位置参数在与第一能量/位置对的位置参数相关联的最小间隔内。 移动站（160）还可以检测第二能量/位置对的能量参数大于第一能量/位置对的能量参数。 因此，移动站（160）可以用第二能量/位置对替换列表上的第一能量/位置对。
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7.发明授权
公开(公告)号：US6078611A
公开(公告)日：2000-06-20
申请号：US931149
申请日：1997-09-16
申请人： Christopher P. La Rosa , Michael J. Carney , Christopher J. Becker , Michael A. Eberhardt , Colin D. Frank , Phillip D. Rasky
发明人： Christopher P. La Rosa , Michael J. Carney , Christopher J. Becker , Michael A. Eberhardt , Colin D. Frank , Phillip D. Rasky
IPC分类号： H04B1/7113 , H04B1/7115 , H04B1/7117 , H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： H04B1/7117 , H04B1/7115 , H04B1/7113
摘要： A RAKE receiver (112) includes a plurality of fingers (122, 124, 126, 128). Each finger includes a demodulator (402) for demodulating a ray of a multipath signal and a time tracking circuit (404) for controlling the time position of the finger in accordance with time position of the ray. A low delay-spread condition is detected and the positions of two adjacent fingers are controlled to prevent convergence of two or more fingers about a common time position. By maintaining finger timing separation, path diversity is exploited by the RAKE receiver even during the low delay-spread condition to improve receiver performance.
摘要翻译： RAKE接收器（112）包括多个指状物（122,124,126,128）。 每个手指包括用于解调多径信号的射线的解调器（402）和用于根据射线的时间位置控制手指的时间位置的时间跟踪电路（404）。 检测到低延迟扩展状态，并且控制两个相邻手指的位置以防止两个或更多个手指围绕公共时间位置的会聚。 通过保持手指定时分离，即使在低延迟扩展条件期间，RAKE接收机也利用路径分集来提高接收机性能。
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公开(公告)号：US20090024901A1
公开(公告)日：2009-01-22
申请号：US11779499
申请日：2007-07-18
IPC分类号： H03M13/03
CPC分类号： H04L27/0012 , H04L27/0008
摘要： A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.
摘要翻译： 解码电路包括响应于突发拒绝信息的混合调制存储器访问电路。 混合调制存储器访问电路选择性地访问包含编码比特的有效突发的突发存储器位置。 混合调制存储器访问电路基于突发拒绝信息选择性地避免访问包含被拒绝的编码比特的突发的突发存储器位置。 在一个示例中，当突发拒绝信息指示存储器位置包含有效突发时，混合调制存储器访问电路访问有效突发。 在一个示例中，当突发拒绝信息指示存储器位置包含拒绝的突发时，混合调制存储器访问电路产生零置信度信息。
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