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    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240355833A1

    公开(公告)日：2024-10-24

    申请号：US18599439

    申请日：2024-03-08

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Takahiko ISHIZU ,  Seiichi YONEDA

    IPC分类号： H01L27/12 ,  H01L29/24 ,  H03K19/003 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

    CPC分类号： H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H03K19/00315 ,  H03K19/017 ,  H03K19/0941 ,  H03K19/20

    摘要： A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

    SIZE SETTING METHOD FOR POWER SWITCH TRANSISTOR AND SYSTEM THEREOF
    2.
    发明公开
    SIZE SETTING METHOD FOR POWER SWITCH TRANSISTOR AND SYSTEM THEREOF 审中-公开

    公开(公告)号：US20230147226A1

    公开(公告)日：2023-05-11

    申请号：US17676882

    申请日：2022-02-22

    申请人： Integrated Silicon Solution Inc.

    发明人： Shuenrun Seara JIAN

    IPC分类号： H03K19/017 ,  H03K19/00

    CPC分类号： H03K19/017 ,  H03K19/0013

    摘要： A size setting method for a power switch transistor and a system thereof are proposed. A load current extracting step is performed to extract a first load current and a second load current. A limited voltage drop calculating step is performed to calculate a limited voltage drop according to a speed proportional value, the first load current and the second load current. A standard supply current calculating step is performed to calculate a standard supply current according to the limited voltage drop. A simulated supply current calculating step is performed to calculate a simulated supply current according to the standard supply current, the limited voltage drop and a line voltage value. A size setting step is performed to compare the first load current with the simulated supply current to calculate a size parameter, and set a size of the power switch transistor according to the size parameter.

    LEVEL SHIFT CIRCUIT AND DISPLAY DRIVER
    4.
    发明申请
    LEVEL SHIFT CIRCUIT AND DISPLAY DRIVER 有权

    公开(公告)号：US20170154568A1

    公开(公告)日：2017-06-01

    申请号：US15361213

    申请日：2016-11-25

    申请人： LAPIS Semiconductor Co., Ltd.

    发明人： Hiroshi TSUCHI

    IPC分类号： G09G3/20 ,  H03K19/017 ,  G11C19/00 ,  H03K19/0185

    CPC分类号： G09G3/2092 ,  G09G2300/043 ,  G09G2300/0809 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/06 ,  G11C19/00 ,  H03K19/017 ,  H03K19/018521

    摘要： A level shift circuit configured to generate an output signal having higher amplitude than that of an input signal. The level shift circuit includes serially-connected first and second level shift circuit for two-step amplitude increase of the input signal. The first level shift circuit includes first to fourth transistors, each of which has a control terminal and first and second current terminals, and first and second resistance elements respectively connected between the first and third transistors, and between the second and fourth transistors. A potential difference between two ends of each resistance element is respectively smaller than, or no smaller than, a respective predetermined potential difference when a current does not flow, or flows, therethrough. The second level shift circuit has fifth to tenth transistors, each of which has a control terminal and first and second current terminals. The output signal is outputted through a connection between the second current terminals of the fifth and ninth transistors.

    DYNAMICALLY ADJUSTABLE CIRCUIT WITH CIRCUIT OF CHARACTERIZED-PATH AND METHOD FOR GENERATING CIRCUIT OF CHARACTERIZED-PATH
    6.
    发明申请
    DYNAMICALLY ADJUSTABLE CIRCUIT WITH CIRCUIT OF CHARACTERIZED-PATH AND METHOD FOR GENERATING CIRCUIT OF CHARACTERIZED-PATH 有权
    具有特征线的电路的动态可调电路以及用于产生特征路径的电路的方法

    公开(公告)号：US20150188541A1

    公开(公告)日：2015-07-02

    申请号：US14569023

    申请日：2014-12-12

    申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    发明人： Kuo-Su HSIAO ,  Chun-Yuan CHENG ,  Chi-Tien SUN

    IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/01

    CPC分类号： H03K19/0008 ,  H03K19/01 ,  H03K19/017

    摘要： An integrated circuit and a method are provided. An integrated circuit comprises a first circuit, with a first character and at least one external control signal, and a character control unit. The character control unit controls the at least one external control signal and has a second circuit, with a second character essentially proportional to the first character, a character adjuster for adjusting the at least one external control signal, and a character monitor for monitoring the operation behavior of the second circuit to control the character adjuster to adjust the at least one external control signal accordingly.

    摘要翻译： 提供集成电路和方法。 集成电路包括具有第一字符和至少一个外部控制信号的第一电路和字符控制单元。 字符控制单元控制至少一个外部控制信号，并且具有第二电路，第二个字符与第一个字符基本成比例;字符调整器，用于调整至少一个外部控制信号;以及字符监视器，用于监视操作 第二电路的行为来控制字符调整器相应地调整至少一个外部控制信号。

    INTEGRATED CIRCUIT FOR MEMORY AND OPERATING METHOD THEREOF
    7.
    发明申请
    INTEGRATED CIRCUIT FOR MEMORY AND OPERATING METHOD THEREOF 有权
    用于存储器的集成电路及其操作方法

    公开(公告)号：US20150123708A1

    公开(公告)日：2015-05-07

    申请号：US14071790

    申请日：2013-11-05

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Chung-Kuang Chen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H03K19/0005 ,  H03K19/017

    摘要： An integrated circuit of a memory is provided. The integrated circuit comprises a first data driving circuit and a transmitting transistor. The first data driving circuit outputs a first data voltage to a first node. The transmitting transistor is coupled between the first node and a second node. When the transmitting transistor receives a bias voltage and the voltage level of the first node is a first voltage level, the transmitting transistor makes the voltage level of the second node to be set as a third voltage level, third voltage level is close to or substantially equal to the first voltage level. When the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independently of the voltage level of the first node.

    摘要翻译： 提供存储器的集成电路。 集成电路包括第一数据驱动电路和发送晶体管。 第一数据驱动电路将第一数据电压输出到第一节点。 发射晶体管耦合在第一节点和第二节点之间。 当发送晶体管接收到偏置电压并且第一节点的电压电平为第一电压电平时，发送晶体管将第二节点的电压电平设置为第三电压电平，第三电压电平接近或基本上 等于第一个电压电平。 当发射晶体管接收偏置电压并且第一节点的电压电平是第二电压电平时，第二节点的电压电平独立于第一节点的电压电平。

    SOURCE DRIVER WITH CHARGE SHARING
    10.
    发明申请
    SOURCE DRIVER WITH CHARGE SHARING 有权
    来源驱动器与充电共享

    公开(公告)号：US20090015297A1

    公开(公告)日：2009-01-15

    申请号：US11866407

    申请日：2007-10-02

    申请人： Chao-An Chen ,  Kuang-Feng Sung

    发明人： Chao-An Chen ,  Kuang-Feng Sung

    IPC分类号： H03K3/00

    CPC分类号： H03K19/0016 ,  H03K19/0019 ,  H03K19/00361 ,  H03K19/017

    摘要： A source driver includes four output switches, two resistors, and a charge-sharing switch. The first output switch and the first resistor are coupled in series to a first output channel of the source driver. The second output switch and the second resistor are coupled in series to a second output channel of the source driver. The third output switch is coupled in parallel to the first output switch. The fourth output switch is coupled in parallel to the second output switch. The charge-sharing switch is coupled between the first resistor and the second resistor. The third output switch and the fourth output switch are controlled to adjust the resistance of the output current path of the source driver.

    摘要翻译： 源极驱动器包括四个输出开关，两个电阻和一个电荷共享开关。 第一输出开关和第一电阻串联耦合到源极驱动器的第一输出通道。 第二输出开关和第二电阻串联耦合到源极驱动器的第二输出通道。 第三输出开关并联到第一输出开关。 第四输出开关并联连接到第二输出开关。 电荷共享开关耦合在第一电阻器和第二电阻器之间。 控制第三输出开关和第四输出开关来调节源极驱动器的输出电流通路的电阻。