公开(公告)号：US20110261620A1

公开(公告)日：2011-10-27

申请号：US13175893

申请日：2011-07-04

申请人： Ping-Chia Shih ,  Chung-Chin Shih

发明人： Ping-Chia Shih ,  Chung-Chin Shih

IPC分类号： G11C14/00

CPC分类号： G11C14/0063

摘要： A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

公开(公告)号：US08018768B2

公开(公告)日：2011-09-13

申请号：US12542711

申请日：2009-08-18

申请人： Ping-Chia Shih ,  Chung-Chin Shih

发明人： Ping-Chia Shih ,  Chung-Chin Shih

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C14/0063

摘要： A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

摘要翻译： 非易失性静态随机存取存储器（NVSRAM）装置包括易失性电路和非易失性电路。 在提供外部电源的正常操作下，易失性电路可以提供快速的数据访问。 当电源以某种方式中断时，非易失性电路可以使用逆变器电路和非易失性可擦除可编程存储器（NVEPM）电路提供数据备份，从而保留先前存储在易失性电路中的数据。

公开(公告)号：US07064031B2

公开(公告)日：2006-06-20

申请号：US10793762

申请日：2004-03-08

申请人： Chung-Chin Shih

发明人： Chung-Chin Shih

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method for forming a semiconductor device by self-aligned is provided. The present method provides a substrate and a multilayer structure is formed thereon. A patterned first layer is formed on the multilayer structure, and a second layer is then formed on the patterned first layer and the multilayer structure. An etching step is performed to partially etch the second layer. A third layer is formed and then is partially removed. Another etching step etches the patterned first layer. The multilayer structure is etched to expose the substrate. The third layer is also etched. A gate layer is formed on the semiconductor device, wherein a plurality of implanted regions are formed inside the substrate not covered by the multilayer structure.

摘要翻译： 提供了通过自对准形成半导体器件的方法。 本方法提供了基板，并且在其上形成多层结构。 在多层结构上形成图案化的第一层，然后在图案化的第一层和多层结构上形成第二层。 执行蚀刻步骤以部分蚀刻第二层。 形成第三层，然后被部分去除。 另一蚀刻步骤蚀刻图案化的第一层。 蚀刻多层结构以露出​​衬底。 第三层也被蚀刻。 在半导体器件上形成栅极层，其中在未被多层结构覆盖的衬底内部形成多个注入区域。

公开(公告)号：US20060109713A1

公开(公告)日：2006-05-25

申请号：US10996204

申请日：2004-11-22

申请人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

发明人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

摘要： A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

摘要翻译： 提供了包括多个字线，多个位线，至少四个控制线和多个存储器单元的存储器件。 位线沿着字线的垂直方向设置。 每个存储单元设置在一条字线和一条位线之间的交叉点，并且具有公共字线的每四个顺序存储单元分别连接到四条控制线。 此外，在每个存储单元中，其控制线设置在其位线和字线之间，并且与其位线平行，其中存储单元中的每一个被设置为位。

公开(公告)号：US20050105332A1

公开(公告)日：2005-05-19

申请号：US10905804

申请日：2005-01-21

申请人： Chung-Chin Shih

发明人： Chung-Chin Shih

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention relates to a memory device and the fabrication method thereof. A plurality of pairs of floating gates and a plurality of pairs of select gates are formed above each active region. After forming a dielectric layer on each floating gate and on each select gate, a plurality of pairs of word lines and a plurality of pairs of source lines are formed simultaneously. The word lines and the source lines are disposed in a direction vertical to the strip active regions. A plurality of source/drain regions is disposed in the substrate beside the word lines and the source lines. After forming a thick dielectric layer over the substrate, a plurality of source line contacts are formed in the thick dielectric layer for connecting the source/drain regions that are between each pair of source lines and at least connecting one of each pair of the source lines.

公开(公告)号：US20110044109A1

公开(公告)日：2011-02-24

申请号：US12542711

申请日：2009-08-18

申请人： Ping-Chia Shih ,  Chung-Chin Shih

发明人： Ping-Chia Shih ,  Chung-Chin Shih

IPC分类号： G11C14/00 ,  G11C5/14

CPC分类号： G11C14/0063

摘要： A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

摘要翻译： 非易失性静态随机存取存储器（NVSRAM）装置包括易失性电路和非易失性电路。 在提供外部电源的正常操作下，易失性电路可以提供快速的数据访问。 当电源以某种方式中断时，非易失性电路可以使用逆变器电路和非易失性可擦除可编程存储器（NVEPM）电路提供数据备份，从而保留先前存储在易失性电路中的数据。

公开(公告)号：US07061040B2

公开(公告)日：2006-06-13

申请号：US10708666

申请日：2004-03-18

申请人： Chung-Chin Shih

发明人： Chung-Chin Shih

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention relates to a memory device and the fabrication method thereof. A plurality of pairs of floating gates and a plurality of pairs of select gates are formed above each active region. After forming a dielectric layer on each floating gate and on each select gate, a plurality of pairs of word lines and a plurality of pairs of source lines are formed simultaneously. The word lines and the source lines are disposed in a direction vertical to the strip active regions. A plurality of source/drain regions is disposed in the substrate beside the word lines and the source lines. After forming a thick dielectric layer over the substrate, a plurality of source line contacts are formed in the thick dielectric layer for connecting the source/drain regions that are between each pair of source lines and at least connecting one of each pair of the source lines.

摘要翻译： 本发明涉及一种存储器件及其制造方法。 在每个有效区域之上形成多对浮动栅极和多对选择栅极。 在每个浮置栅极和每个选择栅极上形成电介质层之后，同时形成多对字线和多对源极线对。 字线和源极线沿垂直于带状有源区的方向设置。 在字线和源极线旁边的基板中设置多个源极/漏极区域。 在衬底上形成厚的电介质层之后，在厚的电介质层中形成多个源极线接触，用于连接在每对源极线之间的源极/漏极区域，并且至少连接每对源极线路之一 。

公开(公告)号：US07123518B2

公开(公告)日：2006-10-17

申请号：US10996204

申请日：2004-11-22

申请人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

发明人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

摘要： A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

摘要翻译： 提供了包括多个字线，多个位线，至少四个控制线和多个存储器单元的存储器件。 位线沿着字线的垂直方向设置。 每个存储单元设置在一条字线和一条位线之间的交叉点，并且具有公共字线的每四个顺序存储单元分别连接到四条控制线。 此外，在每个存储单元中，其控制线设置在其位线和字线之间，并且与其位线平行，其中存储单元中的每一个被设置为位。

公开(公告)号：US20050196948A1

公开(公告)日：2005-09-08

申请号：US10793762

申请日：2004-03-08

申请人： Chung-Chin Shih

发明人： Chung-Chin Shih

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： A method for forming a semiconductor device by self-aligned is provided. The present method provides a substrate and a multilayer structure formed on the substrate. A patterned first layer is formed on the multilayer structure, and a second layer is then formed on the patterned first layer and the multilayer structure. An etching step is performed to partially etch the second layer. A third layer is formed and then is partially removed. Another etching step etches the patterned first layer. The multilayer structure is etched to expose the substrate. The third layer is also etched. A gate layer is formed on the semiconductor device, wherein a plurality of implanted regions are formed inside the substrate not covered by the multilayer structure.

摘要翻译： 提供了通过自对准形成半导体器件的方法。 本方法提供了在基板上形成的基板和多层结构。 在多层结构上形成图案化的第一层，然后在图案化的第一层和多层结构上形成第二层。 执行蚀刻步骤以部分蚀刻第二层。 形成第三层，然后被部分去除。 另一蚀刻步骤蚀刻图案化的第一层。 蚀刻多层结构以露出​​衬底。 第三层也被蚀刻。 在半导体器件上形成栅极层，其中在未被多层结构覆盖的衬底内部形成多个注入区域。

公开(公告)号：US20050106818A1

公开(公告)日：2005-05-19

申请号：US10707016

申请日：2003-11-14

申请人： Chung-Chin Shih

发明人： Chung-Chin Shih

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention relates to a memory device and the fabrication method thereof. A plurality of pairs of floating gates and a plurality of pairs of select gates are formed above each active region. After forming a dielectric layer on each floating gate and on each select gate, a plurality of pairs of word lines and a plurality of pairs of source lines are formed simultaneously. The word lines and the source lines are disposed in a direction vertical to the strip active regions. A plurality of source/drain regions is disposed in the substrate beside the word lines and the source lines. After forming a thick dielectric layer over the substrate, a plurality of source line contacts are formed in the thick dielectric layer for connecting the source/drain regions that are between each pair of source lines and at least connecting one of each pair of the source lines.

摘要翻译： 本发明涉及一种存储器件及其制造方法。 在每个有效区域之上形成多对浮动栅极和多对选择栅极。 在每个浮置栅极和每个选择栅极上形成电介质层之后，同时形成多对字线和多对源极线对。 字线和源极线沿垂直于带状有源区的方向设置。 在字线和源极线旁边的基板中设置多个源极/漏极区域。 在衬底上形成厚的电介质层之后，在厚的电介质层中形成多个源极线接触，用于连接在每对源极线之间的源极/漏极区域，并且至少连接每对源极线路之一 。