公开(公告)号：US07511329B2

公开(公告)日：2009-03-31

申请号：US10906535

申请日：2005-02-24

申请人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

发明人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

摘要翻译： 非易失性存储器包括基板，位于基板上的多个数据存储元件，位于数据存储元件上方的多个控制栅极，位于控制栅极的表面和侧壁上的绝缘层，以及位线 位于绝缘层上以跨越控制门。

公开(公告)号：US20060109713A1

公开(公告)日：2006-05-25

申请号：US10996204

申请日：2004-11-22

申请人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

发明人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

摘要： A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

摘要翻译： 提供了包括多个字线，多个位线，至少四个控制线和多个存储器单元的存储器件。 位线沿着字线的垂直方向设置。 每个存储单元设置在一条字线和一条位线之间的交叉点，并且具有公共字线的每四个顺序存储单元分别连接到四条控制线。 此外，在每个存储单元中，其控制线设置在其位线和字线之间，并且与其位线平行，其中存储单元中的每一个被设置为位。

公开(公告)号：US07123518B2

公开(公告)日：2006-10-17

申请号：US10996204

申请日：2004-11-22

申请人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

发明人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

摘要： A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

摘要翻译： 提供了包括多个字线，多个位线，至少四个控制线和多个存储器单元的存储器件。 位线沿着字线的垂直方向设置。 每个存储单元设置在一条字线和一条位线之间的交叉点，并且具有公共字线的每四个顺序存储单元分别连接到四条控制线。 此外，在每个存储单元中，其控制线设置在其位线和字线之间，并且与其位线平行，其中存储单元中的每一个被设置为位。

公开(公告)号：US06894364B2

公开(公告)日：2005-05-17

申请号：US10248833

申请日：2003-02-24

申请人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

发明人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

摘要翻译： 描述了在互连系统中具有电容器的集成器件的制造方法。 至少第一露出金属线和第二金属线设置在绝缘层中。 堆叠层并图案化以在第二金属线上形成膜堆叠结构。 在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。 至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

公开(公告)号：US06306708B1

公开(公告)日：2001-10-23

申请号：US09496892

申请日：2000-02-02

申请人： Nai-Chen Peng

发明人： Nai-Chen Peng

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method is used to fabricate an electrically erasable programmable read only memory. First, a substrate is provided. Then, a doped polysilicon pillar is formed on the substrate. Furthermore, a source is formed in the substrate beneath the doped polysilicon pillar. Finally, the other structures of the memory are completed in sequence.

摘要翻译： 一种方法用于制造电可擦除可编程只读存储器。 首先，提供基板。 然后，在衬底上形成掺杂多晶硅柱。 此外，在掺杂多晶硅柱下方的衬底中形成源极。 最后，存储器的其他结构依次完成。

公开(公告)号：US06221731B1

公开(公告)日：2001-04-24

申请号：US09063022

申请日：1998-04-20

申请人： Nai-Chen Peng ,  Ming-Tzong Yang

发明人： Nai-Chen Peng ,  Ming-Tzong Yang

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/76213

摘要： A process is disclosed for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout. The buried diffusion is free from being inadvertently cut apart to cause open-circuiting. A bird's beak oxide layer is formed protecting the buried diffusion junction region from undesirable etching, thereby preventing from damaging consumption by etching. The buried diffusion junctions formed may serve as the source/drain region for the transistor.

摘要翻译： 公开了一种用于制造掩埋扩散结的方法，其可以与用于存储器件单元晶体管的浅沟槽隔离组合，其中结和隔离可以以相同的布局形成。 埋入的扩散层不会被无意间切开，导致开路。 形成鸟的喙状氧化物层，以保护掩埋的扩散连接区域免受不希望的蚀刻，从而防止蚀刻损耗。 所形成的掩埋扩散结可以用作晶体管的源极/漏极区域。

公开(公告)号：US20060208306A1

公开(公告)日：2006-09-21

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US06878988B1

公开(公告)日：2005-04-12

申请号：US10709854

申请日：2004-06-02

申请人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

发明人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/792

摘要： An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

摘要翻译： 提供电可编程的非易失性存储单元。 制备半导体衬底。 在半导体衬底上限定一对间隔开的源极/漏极（S / D）区域。 间隔开的S / D区域在其间限定通道区域。 诸如二氧化硅的第一电介质层设置在S / D区域上。 辅助栅极层叠在第一电介质层上。 辅助门具有顶表面和侧壁。 包括电荷捕获层的第二介电层均匀地设置在辅助栅极的顶表面和侧壁上，并且还设置在沟道区上。 第二电介质层在S / D区域之间提供凹槽。 导电栅极材料填充凹槽以控制所述沟道区域。

公开(公告)号：US6133110A

公开(公告)日：2000-10-17

申请号：US127998

申请日：1998-07-31

申请人： Nai-Chen Peng

发明人： Nai-Chen Peng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/82 ,  H01L28/92 ,  H01L27/10852

摘要： A method of manufacturing a dual cylinder-shaped capacitor. The method includes the steps of forming a cylindrical oxide layer above a conductive layer, and then forming silicon nitride spacers and first oxide spacers on the sidewalls of the cylindrical oxide layer. Next, using the silicon nitride spacers, the first oxide spacers and the cylindrical oxide layer as a hard mask, the conductive layer is etched to form a separate lower electrode. Thereafter, the oxide layer is removed so that only the silicon nitride spacers remain. Subsequently, second oxide spacers and third oxide spacers are formed on the sidewalls of the silicon nitride spacers. Finally, the silicon nitride spacers are removed, and then the conductive layer is again etched to form the dual cylinder-shaped lower electrode.

摘要翻译： 一种制造双圆柱形电容器的方法。 该方法包括以下步骤：在导电层上形成圆柱形氧化物层，然后在圆柱形氧化物层的侧壁上形成氮化硅间隔物和第一氧化物间隔物。 接下来，使用氮化硅间隔物，第一氧化物间隔物和圆筒形氧化物层作为硬掩模，对导电层进行蚀刻以形成单独的下电极。 此后，去除氧化物层，使得只剩下氮化硅间隔物。 随后，在氮化硅间隔物的侧壁上形成第二氧化物间隔物和第三氧化物间隔物。 最后，去除氮化硅间隔物，然后再次蚀刻导电层以形成双圆柱形下电极。

公开(公告)号：US5836772A

公开(公告)日：1998-11-17

申请号：US829028

申请日：1997-03-31

申请人： Yun Chang ,  Fuchia Shone ,  Chin-Yi Huang ,  Nai chen Peng

发明人： Yun Chang ,  Fuchia Shone ,  Chin-Yi Huang ,  Nai chen Peng

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8247

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L29/511

摘要： A process is provided for fabricating a nonvolatile memory cell. According to the process, source and drain regions are formed on a first conductivity-type semiconductor substrate; and insulating layer is formed on the source and drain regions; a floating gate is formed on the insulating layer; a dielectric composite is formed on the floating gate; and a control gate is formed on the dielectric composite. The dielectric composite includes a bottom layer of silicon dioxide formed on the floating gate; a layer of silicon nitride formed on the bottom silicon dioxide layer; and a top layer of silicon dioxide formed on the nitride layer such that the silicon nitride layer of the composite is thinner than the top or the bottom silicon dioxide layer.

摘要翻译： 提供了制造非易失性存储单元的过程。 根据该工艺，源极和漏极区域形成在第一导电型半导体衬底上; 并且在源区和漏区上形成绝缘层; 在绝缘层上形成浮栅; 在浮动栅极上形成介电复合材料; 并且在电介质复合体上形成控制栅极。 介电复合材料包括在浮栅上形成的二氧化硅底层; 形成在底部二氧化硅层上的一层氮化硅; 以及形成在氮化物层上的顶层二氧化硅，使得复合材料的氮化硅层比顶部或底部二氧化硅层薄。