公开(公告)号：US20070035900A1

公开(公告)日：2007-02-15

申请号：US11202275

申请日：2005-08-11

申请人： Andrew Huber ,  Ciaran Brennan ,  Paul Dunn ,  Scott Gould ,  Lin Lin ,  Erich Schanzenbach

发明人： Andrew Huber ,  Ciaran Brennan ,  Paul Dunn ,  Scott Gould ,  Lin Lin ,  Erich Schanzenbach

IPC分类号： H02H9/00

CPC分类号： G06F17/5068

摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

摘要翻译： 描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。 电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。 信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。 这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。 对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构 功率区域约束。 创建这些局部电网结构的说明将传递给自动电力布线工具。

公开(公告)号：US20050138496A1

公开(公告)日：2005-06-23

申请号：US10725668

申请日：2003-12-02

申请人： Ciaran Brennan ,  Steven Eustis ,  Michael Fragano ,  Michael Ouellette ,  Neelesh Pai ,  Jeremy Rowland ,  Kevin Tompsett ,  David Wager

发明人： Ciaran Brennan ,  Steven Eustis ,  Michael Fragano ,  Michael Ouellette ,  Neelesh Pai ,  Jeremy Rowland ,  Kevin Tompsett ,  David Wager

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/44

CPC分类号： G11C29/4401 ,  G11C11/41 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0401

摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

摘要翻译： 一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。 在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。 识别至少一个弱记忆体单元。 至少一个弱记忆体被修复。 第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。

公开(公告)号：US20060075368A1

公开(公告)日：2006-04-06

申请号：US10711633

申请日：2004-09-29

申请人： Lu'ay Bakir ,  Ciaran Brennan ,  Joseph Kozhaya ,  Robert Proctor

发明人： Lu'ay Bakir ,  Ciaran Brennan ,  Joseph Kozhaya ,  Robert Proctor

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.

摘要翻译： 公开了一种在集成电路器件内放置静电放电钳的方法。 最初在集成电路设计中定义了一个区域。 然后产生位于限定区域内的ESD敏感电路的列表。 位于限定区域内的ESD敏感电路的重心位于该位置。 接下来，将ESD保护装置置于位于限定区域内的ESD敏感电路的重心处。 确定ESD敏感电路列表内的所有ESD敏感电路是否通过ESD保护装置的放置来保护。 如果是这样，则在其他区域重复该过程，直到整个集成电路被寻址。 否则，将定义的区域划分为至少两个较小的区域，并重复该过程。