公开(公告)号：US20070109851A1

公开(公告)日：2007-05-17

申请号：US11621095

申请日：2007-01-08

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： G11C16/04

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有堆叠栅极结构的衬底。 每个堆叠栅极结构包括选择栅极介电层，选择栅极和盖层。 源极区和漏极区形成在衬底中。 源极区域和漏极区域通过至少两个堆叠的栅极结构彼此分离。 在衬底上形成隧穿电介质层，然后在隧道电介质层上形成第一导电层。 图案化第一导电层以在堆叠栅极结构之间的间隙中形成浮栅。 在衬底上形成栅极间电介质层之后，在衬底上形成第二导电层。 图案化第二导电层以在相邻的堆叠栅极结构之间的间隙中形成相互连接的控制栅极。

公开(公告)号：US07183606B2

公开(公告)日：2007-02-27

申请号：US11160743

申请日：2005-07-07

申请人： Leo Wang ,  Chien-Chih Du ,  Da Sung ,  Chen-Chiu Hsue

发明人： Leo Wang ,  Chien-Chih Du ,  Da Sung ,  Chen-Chiu Hsue

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell including a p-type substrate, an n-type deep well, a stacked gate structure, a source region, a drain region, a p-type pocket doped region, spacers, a p-type doped region and a contact plug is provided. The n-type deep well is set up within the p-type substrate and the stacked gate structure is set up over the p-type substrate. The stacked gate structure further includes a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, a control gate and a cap layer sequentially formed over the p-type substrate. The source region and the drain region are set up in the p-type substrate on each side of the stacked gate structure. The p-type pocket doped region is set up within the n-type deep well region and extends from the drain region to an area underneath the stacked gate structure adjacent to the source region. The spacers are attached to the sidewalls of the stacked gate structure. The p-type doped region is set up within the drain region. The p-type doped region passes through the junction between the drain region and the p-type pocket doped region but is separated from the spacer by a distance. The contact plug is set up over the drain region and is electrically connected to the p-type doped region.

摘要翻译： 一种闪存单元，包括p型衬底，n型深阱，堆叠栅极结构，源极区，漏极区，p型杂质掺杂区，间隔物，p型掺杂区和接触 提供插头。 在p型衬底内设置n型深阱，并且将堆叠的栅极结构设置在p型衬底上。 层叠栅极结构还包括依次形成在p型衬底上的隧道氧化物层，浮栅，栅极间电介质层，控制栅极和覆盖层。 源极区域和漏极区域设置在堆叠栅极结构的每一侧的p型衬底中。 p型腔掺杂区域被设置在n型深阱区域内，并且从漏极区域延伸到邻近源极区域的堆叠栅极结构下面的区域。 间隔件附接到堆叠的栅极结构的侧壁。 p型掺杂区域设置在漏极区域内。 p型掺杂区域通过漏极区域和p型掺杂掺杂区域之间的结，但是与间隔物分离一段距离。 接触插塞设置在漏极区域上并与p型掺杂区域电连接。

公开(公告)号：US20050253182A1

公开(公告)日：2005-11-17

申请号：US10904478

申请日：2004-11-12

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

摘要翻译： 提供非易失性存储器。 在基板上形成多个堆叠的栅极结构。 堆叠的栅极结构包括从衬底表面向上的选择栅极电介质层，选择栅极和覆盖层。 间隔件设置在堆叠的栅极结构的侧壁上。 控制栅极设置在填充层叠栅极结构之间的空间的衬底上，并且彼此连接在一起。 浮置栅极位于堆叠的栅极结构之间并且位于控制栅极和衬底之间。 栅极间电介质层设置在控制栅极和浮栅之间。 隧道电介质层设置在浮置栅极和衬底之间。 源极/漏极区域设置在两个最外层叠的栅极结构之外的衬底中。

公开(公告)号：US20050227434A1

公开(公告)日：2005-10-13

申请号：US10710672

申请日：2004-07-28

申请人： Sheng Wu ,  Da Sung

发明人： Sheng Wu ,  Da Sung

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： A method of manufacturing a non-volatile memory cell is described. The method includes forming a first dielectric layer on a substrate and then forming a patterned mask layer with a trench on the first dielectric layer. A pair of charge storage spacers is formed on the sidewalls of the trench. The patterned mask layer is removed and then a second dielectric is formed on the substrate covering the pair of charge storage spacers. A conductive layer is formed on the second dielectric layer and subsequently patterned to form a gate structure on the pair of charge storage spacers. Portions of the second and first dielectric layers outside the gate structure are removed and then a source/drain region is formed in the substrate on each side of the conductive gate structure.

摘要翻译： 描述了制造非易失性存储单元的方法。 该方法包括在衬底上形成第一电介质层，然后在第一介电层上形成具有沟槽的图案化掩模层。 在沟槽的侧壁上形成一对电荷存储间隔物。 去除图案化的掩模层，然后在覆盖一对电荷存储间隔物的基板上形成第二电介质。 导电层形成在第二介电层上，随后被图案化以在该对电荷存储间隔物上形成栅极结构。 去除栅极结构外部的第二和第一电介质层的部分，然后在导电栅极结构的每一侧上的衬底中形成源/漏区。

公开(公告)号：US20050090057A1

公开(公告)日：2005-04-28

申请号：US10904514

申请日：2004-11-15

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung ,  Chien-Chih Du

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung ,  Chien-Chih Du

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.

摘要翻译： 一种形成闪存单元的方法。 在衬底上形成隧道氧化物层，浮栅层和电介质层。 在电介质层上形成控制栅极层，然后蚀刻形成两个控制栅极。 控制栅极被氧化以在控制栅极的表面上形成多个第二氧化物层，并且在控制栅极之外。 通过利用第二氧化物层作为掩模来蚀刻电介质层和浮栅，以在每个控制栅下方形成浮栅。 在浮动栅极之间形成源极。 浮置栅极和衬底被氧化以在浮置栅极之外形成多个第一氧化物层并在源的表面上形成第三氧化物层。

公开(公告)号：US06855599B2

公开(公告)日：2005-02-15

申请号：US10707668

申请日：2003-12-31

申请人： Chih-Wei Hung ,  Da Sung ,  Chih-Ming Chen

发明人： Chih-Wei Hung ,  Da Sung ,  Chih-Ming Chen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.

摘要翻译： 闪速存储器件包括具有沟槽的衬底，衬底中的深N型阱区，衬底上的堆叠栅极结构，层叠栅极的侧壁上的第一和第二间隔物，其中第一间隔物连接 在沟槽的顶部，在第一间隔物下面的衬底中的源极区域，在第二间隔物下方的衬底中的漏极区域，堆叠栅极和深N型阱区域之间的P型阱区域，其中 两个阱区之间的接合点高于沟槽的底部，沿着沟槽的底部和侧壁的掺杂区域，其中该掺杂区域与源极区域连接并且将P型阱区域与形成的接触部分离开 在沟槽中，触点电连接到源极区域。

公开(公告)号：US07485529B2

公开(公告)日：2009-02-03

申请号：US11621095

申请日：2007-01-08

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有堆叠栅极结构的衬底。 每个堆叠栅极结构包括选择栅极介电层，选择栅极和盖层。 源极区和漏极区形成在衬底中。 源极区域和漏极区域通过至少两个堆叠的栅极结构彼此分离。 在衬底上形成隧穿电介质层，然后在隧道电介质层上形成第一导电层。 图案化第一导电层以在堆叠栅极结构之间的间隙中形成浮栅。 在衬底上形成栅极间电介质层之后，在衬底上形成第二导电层。 图案化第二导电层以在相邻的堆叠栅极结构之间的间隙中形成相互连接的控制栅极。

公开(公告)号：US07436707B2

公开(公告)日：2008-10-14

申请号：US11160693

申请日：2005-07-06

申请人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7885

摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

摘要翻译： 闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。 衬底具有堆叠栅极。 选择栅极形成在衬底上并且与堆叠栅极相邻。 第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。 浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。 用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。 掺杂源区形成在浅二次掺杂区的一侧作为源。

公开(公告)号：US07180128B2

公开(公告)日：2007-02-20

申请号：US10904478

申请日：2004-11-12

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/331

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

摘要翻译： 提供非易失性存储器。 在基板上形成多个堆叠的栅极结构。 堆叠的栅极结构包括从衬底表面向上的选择栅极电介质层，选择栅极和覆盖层。 间隔件设置在堆叠的栅极结构的侧壁上。 控制栅极设置在填充层叠栅极结构之间的空间的衬底上，并且彼此连接在一起。 浮置栅极位于堆叠的栅极结构之间并且位于控制栅极和衬底之间。 栅极间电介质层设置在控制栅极和浮栅之间。 隧道电介质层设置在浮置栅极和衬底之间。 源极/漏极区域设置在两个最外层叠的栅极结构之外的衬底中。

公开(公告)号：US20060110882A1

公开(公告)日：2006-05-25

申请号：US11162533

申请日：2005-09-14

申请人： Chen-Chiang Liu ,  Da Sung ,  Hsin-Ying Tung

发明人： Chen-Chiang Liu ,  Da Sung ,  Hsin-Ying Tung

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/40114

摘要： A method of forming a gate structure, including forming sequentially a gate dielectric layer, a conductive layer, a protective layer, a sacrificial layer, and a patterned mask layer over a substrate. The exposed sacrificial layer is removed by using the patterned mask layer as an etching mask and the protective layer as an etching stop layer. Spacers are formed on the sidewalls of the sacrificial layer. Subsequently, the exposed protective layer and the conductive layer are removed by using the spacers and the sacrificial layer as etching masks, so as to form gate structures. By forming the protective layer on the conductive layer, the present invention can avoid the top surface of each gate structure from generating sharp corners and also increase the width of each gate structure.

摘要翻译： 一种形成栅极结构的方法，包括在衬底上依次形成栅极电介质层，导电层，保护层，牺牲层和图案化掩模层。 通过使用图案化掩模层作为蚀刻掩模和保护层作为蚀刻停止层来去除曝光的牺牲层。 隔板形成在牺牲层的侧壁上。 随后，通过使用间隔物和牺牲层作为蚀刻掩模来去除暴露的保护层和导电层，从而形成栅极结构。 通过在导电层上形成保护层，本发明可以避免每个栅极结构的顶表面产生尖角并且还增加每个栅极结构的宽度。