公开(公告)号：US06963105B2

公开(公告)日：2005-11-08

申请号：US10605419

申请日：2003-09-30

申请人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7885

摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

摘要翻译： 闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。 衬底具有堆叠栅极。 选择栅极形成在衬底上并且与堆叠栅极相邻。 第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。 浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。 用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。 掺杂源区形成在浅二次掺杂区的一侧作为源。

公开(公告)号：US07485529B2

公开(公告)日：2009-02-03

申请号：US11621095

申请日：2007-01-08

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有堆叠栅极结构的衬底。 每个堆叠栅极结构包括选择栅极介电层，选择栅极和盖层。 源极区和漏极区形成在衬底中。 源极区域和漏极区域通过至少两个堆叠的栅极结构彼此分离。 在衬底上形成隧穿电介质层，然后在隧道电介质层上形成第一导电层。 图案化第一导电层以在堆叠栅极结构之间的间隙中形成浮栅。 在衬底上形成栅极间电介质层之后，在衬底上形成第二导电层。 图案化第二导电层以在相邻的堆叠栅极结构之间的间隙中形成相互连接的控制栅极。

公开(公告)号：US07436707B2

公开(公告)日：2008-10-14

申请号：US11160693

申请日：2005-07-06

申请人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7885

摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

摘要翻译： 闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。 衬底具有堆叠栅极。 选择栅极形成在衬底上并且与堆叠栅极相邻。 第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。 浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。 用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。 掺杂源区形成在浅二次掺杂区的一侧作为源。

公开(公告)号：US07180128B2

公开(公告)日：2007-02-20

申请号：US10904478

申请日：2004-11-12

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/331

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

摘要翻译： 提供非易失性存储器。 在基板上形成多个堆叠的栅极结构。 堆叠的栅极结构包括从衬底表面向上的选择栅极电介质层，选择栅极和覆盖层。 间隔件设置在堆叠的栅极结构的侧壁上。 控制栅极设置在填充层叠栅极结构之间的空间的衬底上，并且彼此连接在一起。 浮置栅极位于堆叠的栅极结构之间并且位于控制栅极和衬底之间。 栅极间电介质层设置在控制栅极和浮栅之间。 隧道电介质层设置在浮置栅极和衬底之间。 源极/漏极区域设置在两个最外层叠的栅极结构之外的衬底中。

公开(公告)号：US20050087892A1

公开(公告)日：2005-04-28

申请号：US10709125

申请日：2004-04-15

申请人： Cheng-Yuan Hsu ,  Chih-Wei Hung ,  Da Sung ,  Min-San Huang

发明人： Cheng-Yuan Hsu ,  Chih-Wei Hung ,  Da Sung ,  Min-San Huang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

摘要： A NAND flash memory cell array including a plurality of memory cell row is provided. Each of memory cell row includes a plurality of memory cells disposed between first selecting transistor and second selecting transistor connected in series. Each memory cell has a tunneling dielectric layer, a floating gate, an inter-gate dielectric, a control gate and source/drain regions. An erase gate is disposed between two adjacent memory cells. A plurality of word lines serve to connect the memory cells in rows. A source line serves to connect the source region of the first transistor in a row, whereas a plurality of bit lines serve to connect the drain region of second transistor in a row. A first selecting gate line and a second selecting gate line serve to connect the gate of the first transistor in a row and the gate of second transistor in a row respectively. A plurality of erase gate lines is connected to the erase gates in a row.

摘要翻译： 提供包括多个存储单元行的NAND快闪存储单元阵列。 每个存储单元行包括设置在串联连接的第一选择晶体管和第二选择晶体管之间的多个存储单元。 每个存储单元具有隧道介电层，浮栅，栅极间电介质，控制栅极和源/漏区。 擦除栅极设置在两个相邻的存储单元之间。 多个字线用于以行的形式连接存储器单元。 源极线用于将第一晶体管的源极区域连接成一行，而多个位线用于将第二晶体管的漏极区域连接成一行。 第一选择栅极线和第二选择栅极线用于分别连接一行中的第一晶体管的栅极和第二晶体管的栅极。 多条擦除栅极线一行连接到擦除栅极。

公开(公告)号：US06875660B2

公开(公告)日：2005-04-05

申请号：US10248867

申请日：2003-02-26

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.

摘要翻译： 提供一种制造闪速存储器的方法。 首先，提供其上具有第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构各自包括介电层，第一导电层和盖层。 在衬底上形成隧道氧化物层，然后在第一导电层的侧壁上形成第一间隔物。 此后，在指定用于形成第一栅极结构和第二栅极结构的侧壁的源极区域的一侧上形成第二导电层。 然后，在指定区域中的基板中形成源极区域。 接下来，在第二导电层上形成栅极间电介质层，然后在源极区域上形成绝缘层。 在第一栅极结构和第二栅极结构之间的区域上形成第三导电层之后，在衬底中形成漏极区。

公开(公告)号：US20090086540A1

公开(公告)日：2009-04-02

申请号：US12331367

申请日：2008-12-09

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： G11C16/12 ,  G11C16/26 ,  G11C16/16

CPC分类号： H01L27/11524 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/7923

摘要： A method of operating a non-volatile memory array is provided. The non-volatile memory array includes a substrate, a number of rows of memory cells, a number of control gate lines, a number of select gate lines, a number of source lines, and a number of drain lines. The operating method includes applying 5V voltage to a selected source line, 1.5V voltage to a selected select gate line, 8V voltage to non-selected select gate lines, 10-12V voltage to a selected control gate line and 0-−2V voltage to non-selected control gate lines and the substrate. The drain lines are grounded so that source-side injection (SSI) is triggered to inject electrons into a floating gate of the selected memory cell in a programming operation.

摘要翻译： 提供了一种操作非易失性存储器阵列的方法。 非易失性存储器阵列包括衬底，多行存储器单元，多个控制栅极线，多个选择栅极线，多个源极线和多个漏极线。 操作方法包括：将5V电压施加到所选择的源极线上，对所选择的选择栅极线施加1.5V电压，将8V电压施加到未选择的选择栅极线，将10-12V电压施加到选定的控制栅极线和0-2V电压 未选择的控制栅极线和衬底。 漏极线接地，以便在编程操作中触发源侧注入（SSI）以将电子注入所选存储单元的浮置栅极。

公开(公告)号：US20080048244A1

公开(公告)日：2008-02-28

申请号：US11930178

申请日：2007-10-31

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115

摘要： A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

摘要翻译： 非易失性存储器包括衬底，堆叠栅极结构，间隔物，控制栅极，复合介电层和源极区域/漏极区域。 每个堆叠栅极结构形成在衬底上并且由选择栅极介电层，选择栅极和覆盖层组成。 间隔件设置在堆叠门结构的侧壁上。 在基板上形成包括底部电介质层，电荷俘获层和上部电介质层的复合电介质层。 填充在堆叠的栅极结构之间的空间中的控制栅极设置在复合介电层上并彼此连接。 源极区域/漏极区域配置在靠近外部两个堆叠栅极结构的衬底中。

公开(公告)号：US07029973B2

公开(公告)日：2006-04-18

申请号：US10904514

申请日：2004-11-15

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung ,  Chien-Chih Du

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung ,  Chien-Chih Du

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of second oxide layers on surfaces of the control gates and aside the control gates. The dielectric layer and the floating gate layer are etched by utilizing the second oxide layers as a mask to form a floating gate underneath each of the control gates. A source is formed between the floating gates. The floating gates and the substrate are oxidized to form a plurality of first oxide layers aside the floating gates and form a third oxide layer on a surface of the source.

摘要翻译： 一种形成闪存单元的方法。 在衬底上形成隧道氧化物层，浮栅层和电介质层。 在电介质层上形成控制栅极层，然后蚀刻形成两个控制栅极。 控制栅极被氧化以在控制栅极的表面上形成多个第二氧化物层，并且在控制栅极之外。 通过利用第二氧化物层作为掩模来蚀刻电介质层和浮栅，以在每个控制栅下方形成浮栅。 在浮动栅极之间形成源极。 浮置栅极和衬底被氧化以在浮置栅极之外形成多个第一氧化物层并在源的表面上形成第三氧化物层。

公开(公告)号：US20050253184A1

公开(公告)日：2005-11-17

申请号：US11160104

申请日：2005-06-09

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115

摘要： A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

摘要翻译： 非易失性存储器包括衬底，堆叠栅极结构，间隔物，控制栅极，复合介电层和源极区域/漏极区域。 每个堆叠栅极结构形成在衬底上并且由选择栅极介电层，选择栅极和覆盖层组成。 间隔件设置在堆叠门结构的侧壁上。 在基板上形成包括底部电介质层，电荷俘获层和上部电介质层的复合电介质层。 填充在堆叠的栅极结构之间的空间中的控制栅极设置在复合介电层上并彼此连接。 源极区域/漏极区域配置在靠近外部两个堆叠栅极结构的衬底中。