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公开(公告)号：US06970341B1
公开(公告)日：2005-11-29
申请号：US10984025
申请日：2004-11-08
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe
IPC: H01G2/20 , H01G4/005 , H01G4/06 , H01G4/228 , H01G4/232 , H01G4/30 , H01G4/32 , H01G4/38 , H01G4/40 , H01G9/042 , H01G9/045
Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
Abstract translation: 单片电容器结构包括介电体内的相对和重叠的板，它们被布置成形成较低频率的较高值的电容器。 其他导电结构位于电介质体内部或其外表面上，并且有效地与较低频率的较高值电容器并联形成较高频率的较低值电容器。 与电介质体集成的组合串联和并联电容器的阵列在集成的，具有成本效益的结构中提供了有效的宽带性能。
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公开(公告)号：US06816356B2
公开(公告)日：2004-11-09
申请号：US10412992
申请日：2003-04-14
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe
IPC: H01G9042
Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
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3.发明授权CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY-SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY-TOLERANT EXTERIOR PADS THROUGH MULTIPLE REDUNDANT VIAS 失效传统体积和外部形式的陶瓷芯片电容器由于使用闭孔式内部导电平台而增加电容量可靠地通过多个冗余VIAS连接到位置稳定的外部垫片公开(公告)号：US06366443B1
公开(公告)日：2002-04-02
申请号：US08987463
申请日：1997-12-09
Applicant: Daniel Devoe , Alan D. Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan D. Devoe , Lambert Devoe
IPC: H01G406
CPC classification number: H01G4/232 , H01G4/228 , H05K1/0306 , H05K1/162
Abstract: A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (ii) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor. The composite structure so created exhibits increased capacitance over that which would alternatively exist should no electrically-connected interior metallization planes be present.
Abstract translation: 陶瓷电容器通常为10密耳至340密耳平方，通常为4-20密耳厚度，具有金属化或焊盘的区域，电连接可以通常形成在两个相对的外表面上，每个都具有至少一个和 通常为两个或更多个金属化平面，接近，通常为0.5密耳，分离。 每个内部金属化平面通过多个冗余通孔连接，优选通过以下方式制成：（i）冲孔，（ii）钻孔，（iii）激光钻孔，或（iv）具有感光性粘合剂的生坯陶瓷片的辐射图案化， 表面垫或痕迹。 通孔是众多的和冗余的，通常在10密耳中心上的2密耳直径，在电容器的整个陶瓷层上方并且穿过电容器的整个陶瓷层，允许（i）易于制造而不精确对准或层之间的配准，以及 （ii）成品电容器中的低等效串联电阻（ESR）。 如此制造的复合结构表现出增加的电容，如果不存在电连接的内部金属化平面，则可能存在电容。 ...不再需要最大限度地实现最佳电容，外部焊盘尺寸适中，位置优越，优选从电容器的边缘取出，以防止环氧树脂粘合剂的芯吸，从而允许四舍五入 电容器的边缘为了抑制切屑。 尽管如此，尺寸较小的焊盘仍然比通过冗余地电连接到每个焊盘的多个通孔大得多，并且通常通过阴燃而容易可靠地电连接。
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公开(公告)号：US20090034155A1
公开(公告)日：2009-02-05
申请号：US12245926
申请日：2008-10-06
Applicant: Daniel Devoe
Inventor： Daniel Devoe
CPC classification number: H01G4/232 , H01G4/30 , H01G4/38 , Y10T29/53174
Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.
Abstract translation: 可安装在基板上的电容器装置具有导电底部引线框架，其具有可安装为基本上平行于基板并与其接触的底板，以及导电顶部引线框架，其具有与底部间隔开的顶板 板和第一过渡部分，其具有连接到顶板的第一端和与第一端相对的第二端，其可电连接到基板。 多层电容器安装在顶板和底板之间。 电容器具有电连接到顶板和底板的相对端端，使得内部电极板基本上不平行于衬底。
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公开(公告)号：US07075776B1
公开(公告)日：2006-07-11
申请号：US11199978
申请日：2005-08-09
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe
Abstract: A monolithic capacitor structure includes opposed and overlapping plates within a dielectric body, which are arranged to form a lower frequency, higher value capacitor. Other conductive structure is located either inside the dielectric body or on an external surface thereof and is effective to form a higher frequency, lower value capacitor in parallel with the lower frequency, higher value capacitor. The resulting array of combined series and parallel capacitors integral with the dielectric body provides effective wideband performance in an integrated, cost-effective structure.
Abstract translation: 单片电容器结构包括介电体内的相对和重叠的板，它们被布置成形成较低频率的较高值的电容器。 其他导电结构位于电介质体内部或其外表面上，并且有效地与较低频率的较高值电容器并联形成较高频率的较低值电容器。 与电介质体集成的组合串联和并联电容器的阵列在集成的，具有成本效益的结构中提供了有效的宽带性能。
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Patent Agency Ranking
公开(公告)号：US06751082B2
公开(公告)日：2004-06-15
申请号：US10375304
申请日：2003-02-27
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe , Hung Trinh
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe , Hung Trinh
IPC: H01G406
CPC classification number: H01G4/232 , H01G4/228 , H01L2224/48091 , H01L2924/19107 , H05K1/0306 , H05K1/162 , H01L2924/00014
Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
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7.发明授权CERAMIC CHIP CAPACITOR OF CONVENTIONAL VOLUME AND EXTERNAL FORM HAVING INCREASED CAPACITANCE FROM USE OF CLOSELY SPACED INTERIOR CONDUCTIVE PLANES RELIABLY CONNECTING TO POSITIONALLY TOLERANT EXTERIOR PADS THROUGH MULTIPLE REDUNDANT VIAS 有权传统体积和外部形式的陶瓷芯片电容器与使用封闭式室内导电平面的电容增加相关，通过多余冗余VIAS可靠地连接到位置稳定的外部垫片公开(公告)号：US06542352B1
公开(公告)日：2003-04-01
申请号：US09875347
申请日：2001-06-06
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe , Hung Trinh
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe , Hung Trinh
IPC: H01G406
CPC classification number: H01G4/232 , H01G4/228 , H01L2224/48091 , H01L2924/19107 , H05K1/0306 , H05K1/162 , H01L2924/00014
Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.
Abstract translation: 包括至少一个内部金属化平面或板的电容器和用于在电容器内形成多个冗余电连接的多个通孔。 提供串联电容器，其具有冗余地电连接到至少两个相应外部板的至少两个内部板。 R-C器件具有多个填充有电阻材料和/或导体材料的冗余通孔，以提供与电容器串联或并联的电阻器。 提供电容器和R-C器件，其具有用于施加电压差的终端。 此外，提供了用于制造单个电容器，多个并联阵列电容器，串联电容器和R-C器件的方法，其中芯片从下向上形成。
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公开(公告)号：US20100053842A1
公开(公告)日：2010-03-04
申请号：US12616533
申请日：2009-11-11
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe
IPC: H01G4/228
CPC classification number: H01G4/232 , H01G4/30 , H01G4/38 , H05K1/0231 , H05K1/181 , H05K3/3421 , H05K2201/10515 , H05K2201/10537 , H05K2201/10636 , H05K2201/10946 , Y02P70/611
Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.
Abstract translation: 可安装在基板的平面上的电容器装置包括导电底板，其适于基本平行于基板平行并且与基板平面电接触;以及第一多层电容器，其具有基本上平行的第一和第二电极板， 到底板，其中第一电极板电连接到底板。 导电顶部引线框架与底板重叠并与底板电隔离。 顶引线框架电连接到第二电极板并且适于在基板的平面处电连接。 底部引线框架可以具有波纹形状，其中波纹形状提供了第一层叠电容器和基板之间的顺应性。 顶部引线框架的一部分可以接触第一层叠电容器的一侧的至少一部分。
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公开(公告)号：US08289675B2
公开(公告)日：2012-10-16
申请号：US12616533
申请日：2009-11-11
Applicant: Daniel Devoe , Alan Devoe , Lambert Devoe
Inventor： Daniel Devoe , Alan Devoe , Lambert Devoe
IPC: H01G4/228
CPC classification number: H01G4/232 , H01G4/30 , H01G4/38 , H05K1/0231 , H05K1/181 , H05K3/3421 , H05K2201/10515 , H05K2201/10537 , H05K2201/10636 , H05K2201/10946 , Y02P70/611
Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.
Abstract translation: 可安装在基板的平面上的电容器装置包括导电底板，其适于基本平行于基板平行并且与基板平面电接触;以及第一多层电容器，其具有基本上平行的第一和第二电极板， 到底板，其中第一电极板电连接到底板。 导电顶部引线框架与底板重叠并与底板电隔离。 顶引线框架电连接到第二电极板并且适于在基板的平面处电连接。 底部引线框架可以具有波纹形状，其中波纹形状提供了第一层叠电容器和基板之间的柔顺性。 顶部引线框架的一部分可以接触第一层叠电容器的一侧的至少一部分。
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公开(公告)号：US07633739B2
公开(公告)日：2009-12-15
申请号：US12245926
申请日：2008-10-06
Applicant: Daniel Devoe
Inventor： Daniel Devoe
CPC classification number: H01G4/232 , H01G4/30 , H01G4/38 , Y10T29/53174
Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.
Abstract translation: 可安装在基板上的电容器装置具有导电底部引线框架，其具有可安装为基本上平行于基板并与其接触的底板，以及导电顶部引线框架，其具有与底部间隔开的顶板 板和第一过渡部分，其具有连接到顶板的第一端和与第一端相对的第二端，其可电连接到基板。 多层电容器安装在顶板和底板之间。 电容器具有电连接到顶板和底板的相对端端，使得内部电极板基本上不平行于衬底。
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