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    Instruction dependency scoreboard with a hierarchical structure
    2.
    发明授权
    Instruction dependency scoreboard with a hierarchical structure 有权
    具有层次结构的指令依赖记分板

    公开(公告)号：US06662293B1

    公开(公告)日：2003-12-09

    申请号：US09577219

    申请日：2000-05-23

    申请人： Richard H. Larson ,  Sanjay Patel ,  Poonacha P. Kongetira ,  Daniel L. Leibholz

    发明人： Richard H. Larson ,  Sanjay Patel ,  Poonacha P. Kongetira ,  Daniel L. Leibholz

    IPC分类号： G06F1500

    CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

    摘要： One embodiment of the present invention provides a system that selects instructions to be executed in a computer system that supports out-of-order execution of program instructions. The system receives dependency information for a first instruction. This dependency information identifies preceding instructions in the execution stream of a program that need to complete before the first instruction can be executed. The system divides this dependency information into a recent set and a less recent set. The recent set includes dependency information for a block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The less recent set includes dependency information for instructions not in the block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The system stores the recent set of dependency information in a first store, and stores the less recent set of dependency information in a second store. The first store is smaller and faster than the second store so that an update to dependency information takes less time to propagate through the first store than the second store. In one embodiment of the present invention, the system receives the dependency information for the first instruction from the first store and the second store, and determines from the dependency information if the first instruction is available to be executed by determining whether all preceding dependencies related to the first instruction have been satisfied. In one embodiment of the present invention, the system selects a second instruction from instructions that are available to be executed, and executes the second instruction.

    摘要翻译： 本发明的一个实施例提供了一种选择要在支持程序指令的无序执行的计算机系统中执行的指令的系统。 系统接收第一条指令的依赖信息。 该依赖性信息识别在可以执行第一指令之前需要完成的程序的执行流中的先前指令。 该系统将此依赖关系信息划分为最近设置和不太近的集合。 最近设置包括在第一指令之前紧接在第一指令之前的指令块的依赖信息，该指令需要在第一指令可执行之前完成。 不太近的集合包括不在紧接在第一指令之前的指令块中的指令的依赖信息，该指令需要在执行第一指令之前完成。 该系统将最新的一组依赖性信息存储在第一个存储中，并将较不新近的一组依赖关系信息存储在第二个存储中。 第一个商店比第二个商店更小和更快，因此对依赖关系信息的更新在第一个商店中传播的时间比第二个商店更少。 在本发明的一个实施例中，系统从第一存储和第二存储器接收第一指令的依赖性信息，并且从依赖信息确定第一指令是否可用于执行，通过确定是否所有先前的依赖关系与 第一条指示已经满足。 在本发明的一个实施例中，系统从可用于执行的指令中选择第二指令，并执行第二指令。

    Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
    3.
    发明授权
    Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor 有权
    用于在无序微处理器中同步多个线程的装置和方法

    公开(公告)号：US07493615B2

    公开(公告)日：2009-02-17

    申请号：US10428597

    申请日：2003-05-01

    申请人： Evan H. Gewirtz ,  Todd D. Basso ,  Daniel L. Leibholz ,  Benjamin C. Cordes

    发明人： Evan H. Gewirtz ,  Todd D. Basso ,  Daniel L. Leibholz ,  Benjamin C. Cordes

    IPC分类号： G06F9/46 ,  G06F7/38

    CPC分类号： G06F9/52 ,  G06F8/458 ,  G06F9/30087 ,  G06F9/3851

    摘要： The present invention generally relates to synchronization of multiple threads in an out-of-order microprocessor utilizing the insertion of a trap. In one embodiment, while synchronizing multiple running threads, an instruction within a first running thread is identified. Upon identification of this instruction, a trap is inserted into a second running thread. All instructions within the instructional pipeline that are scheduled for execution prior to this trapped instruction must retire before the subsequent execution of the synchronizing instruction. Following the execution of the synchronizing instruction, all instructions within the instruction pipeline slated for execution after the trapped instruction in the remaining threads are flushed and refetched.

    摘要翻译： 本发明一般涉及使用陷阱的插入在不规则的微处理器中同步多个线程。 在一个实施例中，在同步多个运行的线程的同时，识别第一运行线程内的指令。 在识别该指令后，将陷阱插入到第二个运行的线程中。 指令管道内的所有指令，在被捕获指令之前被调度执行必须在后续执行同步指令之前退出。 在执行同步指令之后，在剩余线程中被捕获的指令之后预定执行的指令流水线内的所有指令被刷新并被刷新。

    Method for compacting an instruction queue
    5.
    发明授权
    Method for compacting an instruction queue 有权
    压缩指令队列的方法

    公开(公告)号：US06704856B1

    公开(公告)日：2004-03-09

    申请号：US09465175

    申请日：1999-12-17

    申请人： James A. Farrell ,  Timothy C. Fischer ,  Daniel L. Leibholz ,  Bruce A. Gieseke

    发明人： James A. Farrell ,  Timothy C. Fischer ,  Daniel L. Leibholz ,  Bruce A. Gieseke

    IPC分类号： G06F930

    CPC分类号： G06F9/3802 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： A method of compacting an instruction queue in an out of order processor includes determining the number of invalid instructions below and including each row in the queue, by counting invalid bits or validity indicators associated with rows below and up to the current row. For each row, multiplexor select signals are generated from the flat vector counts for the N rows above and including the present row, and from the validity indicators associated with the N rows, where N is a predetermined value. A multiplexor associated with a particular row selects one of the N rows according to the select value, and moves or passes the instruction held in the selected row to the present row. A row's select value is determined by forming a diagonal from the N count vectors corresponding to the N rows above and including the present row, and logically ANDing, each diagonal bit with the valid bit associated with the same row. Each row's count vector is determined in two stages. In the first stage, a local count is determined for each row in a local group of rows, and a global count is determined for the entire local group. Each local count is determined by counting the validity indicators associated with rows in the local group. In the second stage, a final count is determined for each row in the queue, by combining the local and global counts generated for the local group in the first stage, with global counts generated in local groups below the local group. The N rows can extend to the queue's input pipeline.

    摘要翻译： 压缩无序处理器中的指令队列的方法包括通过计数与当前行下方的行相关联的无效位或有效性指示符，来确定队列中每行的无效指令的数量，并且包括每行。 对于每一行，多路复用器选择信号从针对当前行上方并包括当前行的N行的平坦向量计数以及与N行相关联的有效指示符生成，其中N是预定值。 与特定行相关联的多路复用器根据选择值选择N行之一，并将所选行中保存的指令移动或传递到当前行。 通过从对应于上述N行并包括当前行的N个计数向量形成对角线来确定行的选择值，并且将每个对角位与逻辑与运算相关联的有效位进行逻辑与运算。 每行的计数向量分两个阶段确定。 在第一阶段，为本地行行中的每一行确定本地计数，并为整个本地组确定全局计数。 每个本地计数通过对与本地组中的行相关联的有效性指示进行计数来确定。 在第二阶段，通过组合在第一阶段为本地组生成的本地和全局计数以及本地组下的本地组中生成的全局计数，确定队列中每一行的最终计数。 N行可以扩​​展到队列的输入管道。