公开(公告)号：US06662293B1

公开(公告)日：2003-12-09

申请号：US09577219

申请日：2000-05-23

申请人： Richard H. Larson ,  Sanjay Patel ,  Poonacha P. Kongetira ,  Daniel L. Leibholz

发明人： Richard H. Larson ,  Sanjay Patel ,  Poonacha P. Kongetira ,  Daniel L. Leibholz

IPC分类号： G06F1500

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： One embodiment of the present invention provides a system that selects instructions to be executed in a computer system that supports out-of-order execution of program instructions. The system receives dependency information for a first instruction. This dependency information identifies preceding instructions in the execution stream of a program that need to complete before the first instruction can be executed. The system divides this dependency information into a recent set and a less recent set. The recent set includes dependency information for a block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The less recent set includes dependency information for instructions not in the block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The system stores the recent set of dependency information in a first store, and stores the less recent set of dependency information in a second store. The first store is smaller and faster than the second store so that an update to dependency information takes less time to propagate through the first store than the second store. In one embodiment of the present invention, the system receives the dependency information for the first instruction from the first store and the second store, and determines from the dependency information if the first instruction is available to be executed by determining whether all preceding dependencies related to the first instruction have been satisfied. In one embodiment of the present invention, the system selects a second instruction from instructions that are available to be executed, and executes the second instruction.

摘要翻译： 本发明的一个实施例提供了一种选择要在支持程序指令的无序执行的计算机系统中执行的指令的系统。 系统接收第一条指令的依赖信息。 该依赖性信息识别在可以执行第一指令之前需要完成的程序的执行流中的先前指令。 该系统将此依赖关系信息划分为最近设置和不太近的集合。 最近设置包括在第一指令之前紧接在第一指令之前的指令块的依赖信息，该指令需要在第一指令可执行之前完成。 不太近的集合包括不在紧接在第一指令之前的指令块中的指令的依赖信息，该指令需要在执行第一指令之前完成。 该系统将最新的一组依赖性信息存储在第一个存储中，并将较不新近的一组依赖关系信息存储在第二个存储中。 第一个商店比第二个商店更小和更快，因此对依赖关系信息的更新在第一个商店中传播的时间比第二个商店更少。 在本发明的一个实施例中，系统从第一存储和第二存储器接收第一指令的依赖性信息，并且从依赖信息确定第一指令是否可用于执行，通过确定是否所有先前的依赖关系与 第一条指示已经满足。 在本发明的一个实施例中，系统从可用于执行的指令中选择第二指令，并执行第二指令。

公开(公告)号：US07136308B2

公开(公告)日：2006-11-14

申请号：US10979345

申请日：2004-11-01

申请人： Shree Kant ,  Kenway Tam ,  Poonacha P. Kongetira ,  Yuan-Jung D Lin ,  Zhen W. Liu ,  Kathirgamar Aingaran

发明人： Shree Kant ,  Kenway Tam ,  Poonacha P. Kongetira ,  Yuan-Jung D Lin ,  Zhen W. Liu ,  Kathirgamar Aingaran

IPC分类号： G11C7/10

CPC分类号： G11C11/419 ,  G11C7/10 ,  G11C7/24

摘要： A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

摘要翻译： 存储器系统包括有源存储电路和至少一个基本存储电路。 至少一个基本存储电路通过至少一个传递门，至少一个驱动器和位线耦合到有源存储电路。 所述至少一个传递门和所述至少一个驱动器具有与所述有源存储电路和所述至少一个基本存储电路中的每个器件的器件尺寸基本相似的器件尺寸。 还描述了在两个存储电路之间交换数据的方法。

公开(公告)号：US06862676B1

公开(公告)日：2005-03-01

申请号：US09761494

申请日：2001-01-16

申请人： Micah C. Knapp ,  Poonacha P. Kongetira ,  Marc E. Lamere ,  Julie M. Staraitis

发明人： Micah C. Knapp ,  Poonacha P. Kongetira ,  Marc E. Lamere ,  Julie M. Staraitis

IPC分类号： G06F9/38 ,  G06F9/34 ,  G06F12/06

CPC分类号： G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

摘要翻译： 呈现具有发送第一和第二输出信号的内容可寻址存储器结构的超标量处理器。 超标量处理器对指令集执行无序处理。 从第一输出信号，可以确定指令集当前获取的指令与先前的飞行中指令之间的依赖关系，并用于为所有飞行中的指令生成依赖矩阵。 从第二输出信号可以确定一旦取消了相关性就执行指令所需的数据的物理寄存器地址。