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公开(公告)号：US08380737B2
公开(公告)日：2013-02-19
申请号：US13233095
申请日：2011-09-15
申请人： Cagri Balkesen , Markus T. Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie C. Scherzinger , Thomas Schwarz
发明人： Cagri Balkesen , Markus T. Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie C. Scherzinger , Thomas Schwarz
CPC分类号： G06F17/10 , G06F7/02 , G06F17/30952
摘要： First and second sets of numbers are received in an input range, which is separated into sub ranges. A first sub range is processed by initializing bits of a memory to a first logical state and by changing the initial state of each of the bits corresponding to a received number of the first set that is within the first sub range. Each number received in the second set is compared to a bit in the memory to identify a set of received numbers that are in the first sub range and that are in both the first set and the second set. The comparing is responsive to detecting a change of initial state of any bit in the memory during the processing of the first sub range. The processing and comparing is repeated for remaining sub ranges to identify received numbers that are in both the sets.
摘要翻译： 在输入范围内接收第一和第二组数字，分成子范围。 通过将存储器的位初始化为第一逻辑状态并且通过改变与在第一子范围内的第一集合的接收号码相对应的每个位的初始状态来处理第一子范围。 将第二组中接收到的每个数字与存储器中的位进行比较，以识别处于第一子范围并且处于第一集合和第二集合中的一组接收号码。 该比较响应于在第一子范围的处理期间检测存储器中任何位的初始状态的变化。 对于剩余子范围重复处理和比较以识别两个集合中的接收数字。
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公开(公告)号：US20110302367A1
公开(公告)日：2011-12-08
申请号：US12962774
申请日：2010-12-08
申请人： Cagri Balkesen , Markus Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie Scherzinger , Thomas Schwarz
发明人： Cagri Balkesen , Markus Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie Scherzinger , Thomas Schwarz
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0215 , G06F12/0897 , Y02D10/13
摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.
摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。
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公开(公告)号：US08495286B2
公开(公告)日：2013-07-23
申请号：US12962774
申请日：2010-12-08
申请人： Cagri Balkesen , Markus Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie Scherzinger , Thomas Schwarz
发明人： Cagri Balkesen , Markus Buehler , Rainer Dorsch , Guenther Hutzl , Michael W. Kaufmann , Daniel Pfefferkorn , David Rohr , Stefanie Scherzinger , Thomas Schwarz
CPC分类号： G06F12/0804 , G06F12/0215 , G06F12/0897 , Y02D10/13
摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.
摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。
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公开(公告)号：US20120158774A1
公开(公告)日：2012-06-21
申请号：US13233095
申请日：2011-09-15
申请人： CAGRI BALKESEN , MARKUS T. BUEHLER , RAINER DORSCH , GUENTHER HUTZL , MICHAEL W. KAUFMANN , DANIEL PFEFFERKORN , DAVID ROHR , STEFANIE C. SCHERZINGER , THOMAS SCHWARZ
发明人： CAGRI BALKESEN , MARKUS T. BUEHLER , RAINER DORSCH , GUENTHER HUTZL , MICHAEL W. KAUFMANN , DANIEL PFEFFERKORN , DAVID ROHR , STEFANIE C. SCHERZINGER , THOMAS SCHWARZ
CPC分类号： G06F17/10 , G06F7/02 , G06F17/30952
摘要： The present invention relates to a computer program product, method and system for computing set intersection of a first and a second unordered set of discrete members that stem from a known input range of consecutive discrete numbers. The method breaks the numbers into subranges and for each subrange, utilizes a bit vector in a first random access memory, directly addressing bits representing values in a subrange in the first set to values in the second set in the subrange and writing each number of the second set that is also set member of the first set in the sub range directly to an output. This may be utilized by various applications including database applications. The algorithm may be offloaded to one or more processing subsystems.
摘要翻译： 本发明涉及一种计算机程序产品，方法和系统，用于计算来自连续离散数字的已知输入范围的离散元件的第一和第二无序组的集合交集。 该方法将数字划分成子范围，并且对于每个子范围，利用第一随机存取存储器中的位向量，直接将表示第一集合中的子范围中的值的位数寻址到子范围中的第二集合中的值，并写入每个子数 第二个集合也将子范围中的第一个集合的成员直接设置为输出。 这可以由包括数据库应用在内的各种应用来使用。 该算法可以被卸载到一个或多个处理子系统。
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